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92 lines
2.4 KiB
Systemverilog
92 lines
2.4 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module tb_daisy_chain();
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logic clk_i, rst_i, ready_i, irq_ret_i;
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logic [15:0] masked_irq_i;
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logic irq_o;
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logic [15:0] irq_ret_o;
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logic [31:0] irq_cause_o;
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daisy_chain DUT(.*);
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initial clk_i = 0;
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always #5 clk_i = !clk_i;
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initial begin
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rst_i <= 1'b1;
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@(posedge clk_i);
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rst_i <= 1'b0;
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mcause_onehot_test();
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random_test();
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$finish();
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end
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task mcause_onehot_test();
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ready_i <= 1'b1;
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masked_irq_i <= 0;
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repeat (2**16) begin
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@(posedge clk_i);
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masked_irq_i <= masked_irq_i + 1'b1;
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end
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endtask
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task random_test();
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repeat(2**16) begin
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@(posedge clk_i);
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ready_i <= $urandom_range(1);
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irq_ret_i <= $urandom_range(1);
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masked_irq_i <= $urandom_range(2**16);
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end
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endtask
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logic [15:0] cause;
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always_ff @(posedge clk_i) begin
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if(rst_i) begin
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cause <= '0;
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end
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else if(irq_o) begin
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cause <= irq_cause_o[19:4];
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end
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end
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irq_ret_o_is_not_0: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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!irq_ret_i |-> irq_ret_o === '0
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)else $error("irq_ret_o are not equal 0");
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irq_ret_o_is_incorrect: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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irq_ret_i |-> irq_ret_o === cause
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)else $error("irq_ret_o are incorrect: %08h", irq_ret_o);
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irq_o_is_not_1: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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ready_i & masked_irq_i |-> irq_o
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)else $error("irq_o are not equal 1");
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irq_o_is_not_0: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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!ready_i |-> !irq_o
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)else $error("irq_o are not equal 0");
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irq_cause_o_mcause: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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irq_o |-> $onehot0(irq_cause_o[19:4])
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)else $error("error value on irq_cause_o: %08h, should be onehot", irq_cause_o[20:5]);
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irq_cause_o_borders: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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irq_o |-> (irq_cause_o[31:20] === 12'h800) && (irq_cause_o[3:0] == 4'h0)
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)else $error("irq_cause_o borders are incorrect: %08h", irq_cause_o);
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endmodule |