mirror of
https://github.com/MPSU/APS.git
synced 2025-09-16 17:40:41 +00:00
34 lines
582 B
Verilog
34 lines
582 B
Verilog
`timescale 1ns / 1ps
|
|
|
|
module tb_miriscv_top();
|
|
|
|
parameter HF_CYCLE = 2.5; // 200 MHz clock
|
|
parameter RST_WAIT = 10; // 10 ns reset
|
|
parameter RAM_SIZE = 512; // in 32-bit words
|
|
|
|
// clock, reset
|
|
reg clk;
|
|
reg rst_n;
|
|
|
|
miriscv_top #(
|
|
.RAM_SIZE ( RAM_SIZE ),
|
|
.RAM_INIT_FILE ( "program_sort.dat" )
|
|
) dut (
|
|
.clk_i ( clk ),
|
|
.rst_n_i ( rst_n )
|
|
);
|
|
|
|
initial begin
|
|
clk = 1'b0;
|
|
rst_n = 1'b0;
|
|
#RST_WAIT;
|
|
rst_n = 1'b1;
|
|
end
|
|
|
|
always begin
|
|
#HF_CYCLE;
|
|
clk = ~clk;
|
|
end
|
|
|
|
endmodule
|