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96 lines
3.7 KiB
Systemverilog
96 lines
3.7 KiB
Systemverilog
`timescale 1ns / 1ps
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module nexys_alu(
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input CLK100,
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input resetn,
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input [15:0] SW,
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output [15:0] LED,
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output CA, CB, CC, CD, CE, CF, CG,
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output [7:0] AN
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);
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import alu_opcodes_pkg::*;
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wire [4:0] operator_i;
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wire [31:0] operand_a_i;
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wire [31:0] operand_b_i;
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wire [31:0] result_o;
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wire comparison_result_o;
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localparam pwm = 1000;
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reg [9:0] counter;
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reg [3:0] semseg;
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reg [7:0] ANreg;
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reg CAr, CBr, CCr, CDr, CEr, CFr, CGr;
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reg [15:0] LEDr;
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reg minus;
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alu_riscv DUT
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(
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.ALUOp (operator_i),
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.A (operand_a_i),
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.B (operand_b_i),
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.Result (result_o),
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.Flag (comparison_result_o)
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);
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assign operator_i = SW[4:0];
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assign operand_b_i = {{28{SW[10]}},SW[9:6]};
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assign operand_a_i = {{28{SW[15]}},SW[14:11]};
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assign LED[15:0] = LEDr[15:0];
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assign AN[7:0] = ANreg[7:0];
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assign {CA, CB, CC, CD, CE, CF, CG} = {CAr, CBr, CCr, CDr, CEr, CFr, CGr};
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initial ANreg[7:0] = 8'b11111110;
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always @(posedge CLK100) begin
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if (!resetn) begin
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LEDr[15:0] <= 'b0;
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counter <= 'b0;
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ANreg[7:0] <= 8'b11111111;
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{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111;
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end
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else begin
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LEDr[14:0] <= result_o[14:0];
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LEDr[15] <= comparison_result_o;
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if (counter < pwm) counter = counter + 'b1;
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else begin
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counter = 'b0;
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ANreg[1] <= ANreg[0];
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ANreg[2] <= ANreg[1];
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ANreg[3] <= ANreg[2];
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ANreg[4] <= ANreg[3];
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ANreg[5] <= ANreg[4];
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ANreg[6] <= ANreg[5];
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ANreg[7] <= ANreg[6];
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ANreg[0] <= !(SW[5] && (ANreg[6:0] == 7'b1111111));
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end
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case (1'b0)
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ANreg[0]: semseg <= result_o[31] ? ( ~result_o + 1 ) % 4'd10: (result_o ) % 4'd10;
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ANreg[1]: semseg <= result_o[31] ? ((~result_o + 1) / 'd10 ) % 4'd10: (result_o / 'd10 ) % 4'd10;
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ANreg[2]: semseg <= result_o[31] ? ((~result_o + 1) / 'd100 ) % 4'd10: (result_o / 'd100 ) % 4'd10;
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ANreg[3]: semseg <= result_o[31] ? ((~result_o + 1) / 'd1000) % 4'd10: (result_o / 'd1000) % 4'd10;
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ANreg[4]: semseg <= operand_b_i[31] ? ( ~operand_b_i + 1 ) % 4'd10: (operand_b_i ) % 4'd10;
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ANreg[5]: semseg <= operand_b_i[31] ? ((~operand_b_i + 1) / 'd10) % 4'd10: (operand_b_i / 'd10) % 4'd10;
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ANreg[6]: semseg <= operand_a_i[31] ? ( ~operand_a_i + 1 ) % 4'd10: (operand_a_i ) % 4'd10;
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ANreg[7]: semseg <= operand_a_i[31] ? ((~operand_a_i + 1) / 'd10) % 4'd10: (operand_a_i / 'd10) % 4'd10;
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endcase
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minus <= (operator_i == ALU_ADD || operator_i == ALU_SUB || operator_i == ALU_SLTS || operator_i == ALU_SRA || operator_i == ALU_LTS || operator_i == ALU_GES);
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case (semseg)
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4'd0: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= (((!ANreg[5] & operand_b_i[31]) || (!ANreg[7] & operand_a_i[31]) || (!ANreg[3] & result_o[31])) && minus) ? 7'b1111110: 7'b0000001;
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4'd1: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= (((!ANreg[5] & operand_b_i[31]) || (!ANreg[7] & operand_a_i[31]) || (!ANreg[3] & result_o[31])) && minus) ? 7'b1001110: 7'b1001111;
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4'd2: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0010010;
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4'd3: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000110;
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4'd4: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001100;
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4'd5: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100100;
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4'd6: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100000;
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4'd7: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001111;
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4'd8: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000000;
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4'd9: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000100;
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endcase
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end
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end
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endmodule |