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4be66525d6
Поскольку студентам не рассказывается что это за конструкция и зачем она используется, они не прописывают таймскейл в своих модулях. Смесь модулей с таймскейлом и без него приводит к появлению множества предупреждений, забивающих лог.
108 lines
2.0 KiB
Systemverilog
108 lines
2.0 KiB
Systemverilog
//////////////////////////////////////////////////////////////////////////////////
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// Company: MIET
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// Engineer: Nikita Bulavin
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//
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// Create Date:
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// Design Name:
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// Module Name: tb_riscv_unit
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// Project Name: RISCV_practicum
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// Target Devices: Nexys A7-100T
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// Tool Versions:
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// Description: tb for peripheral units
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_riscv_unit();
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localparam variant = 'd1; //1-SW_LED; 2-PS2_HEXLED; 3-UART;
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localparam button = 8'h16; //keyboard key code
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logic clk;
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logic ps2_clk;
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logic ps2_dat;
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logic resetn;
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logic [15:0] sw_i;
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logic [15:0] led_o;
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logic parity;
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logic starter;
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logic [ 6:0] hex_led_o;
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logic [ 7:0] hex_sel_o;
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logic rx_i;
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logic tx_o;
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initial begin clk = 0; ps2_clk = 0; end
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always #50 clk = ~clk;
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always #50000 if (variant == 2) if(starter || (cntr > 0)) ps2_clk = ~ps2_clk; else ps2_clk = 1;
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logic [11:0] data;
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initial begin
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resetn = 1;
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repeat(2)@(posedge clk);
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resetn = 0;
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repeat(2) @(posedge clk);
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resetn = 1;
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end
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riscv_unit dut(
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.clk_i (clk ),
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.resetn_i (resetn ),
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.sw_i (sw_i ),
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.led_o (led_o ),
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.kclk_i (ps2_clk ),
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.kdata_i (ps2_dat ),
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.hex_led_o(hex_led_o),
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.hex_sel_o(hex_sel_o),
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.rx_i (rx_i ),
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.tx_o (tx_o )
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);
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logic [3:0] cntr;
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always @(negedge ps2_clk) begin
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if(starter || (cntr > 0))
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if(cntr == 10)
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cntr <= 0;
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else
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cntr <= cntr + 1;
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end
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assign ps2_dat = cntr>0? data[cntr-1] : 1;
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initial begin
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sw_i = 16'h0;
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cntr = 0;
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starter = 0;
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parity = !(^button);
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data = 0;
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case (variant)
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1: begin
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#10000;
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sw_i = 16'h01AA;
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#20000;
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sw_i = 16'hFF00;
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end
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2: begin
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data = {2'b11, parity, button, 1'b0};
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#100000;
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starter = 1;
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@(posedge ps2_clk)
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starter = 0;
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end
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3: begin
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end
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endcase
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end
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endmodule
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