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4be66525d6
Поскольку студентам не рассказывается что это за конструкция и зачем она используется, они не прописывают таймскейл в своих модулях. Смесь модулей с таймскейлом и без него приводит к появлению множества предупреждений, забивающих лог.
76 lines
2.2 KiB
Systemverilog
76 lines
2.2 KiB
Systemverilog
module nexys_CYBERcobra(
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input CLK100,
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input resetn,
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input BTND,
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input [15:0] SW,
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output CA, CB, CC, CD, CE, CF, CG,
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output [7:0] AN
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);
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CYBERcobra dut(
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.clk_i(CLK100),
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.rst_i(!resetn),
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.sw_i({7'b0,splash,SW[7:0]}),
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.out_o(out)
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);
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localparam pwm = 1000;
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reg [9:0] counter;
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reg [3:0] semseg;
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reg [7:0] ANreg;
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reg CAr, CBr, CCr, CDr, CEr, CFr, CGr;
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reg [3:0] btn;
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reg [10:0] btn_reg;
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wire splash;
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wire [31:0] out;
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assign AN[7:0] = ANreg[7:0];
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assign {CA, CB, CC, CD, CE, CF, CG} = {CAr, CBr, CCr, CDr, CEr, CFr, CGr};
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assign splash = ((btn == 4'b1111) ^ btn_reg[10]) && (btn == 4'b1111);
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always @(posedge CLK100) begin
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if (!resetn) begin
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counter <= 'b0;
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ANreg[7:0] <= 8'b11111111;
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{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111;
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btn <= 4'b0;
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btn_reg <= 0;
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end
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else begin
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btn <= (btn << 1'b1) + BTND;
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btn_reg <= (btn_reg << 1'b1) + (btn == 4'b1111);
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if (counter < pwm) counter = counter + 'b1;
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else begin
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counter = 'b0;
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ANreg[1] <= ANreg[0];
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ANreg[2] <= ANreg[1];
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ANreg[3] <= ANreg[2];
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ANreg[4] <= ANreg[3];
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ANreg[5] <= ANreg[4];
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ANreg[6] <= ANreg[5];
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ANreg[7] <= ANreg[6];
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ANreg[0] <= !(ANreg[6:0] == 7'b1111111);
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end
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case (1'b0)
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ANreg[0]: semseg <= out[3 : 0];
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ANreg[1]: semseg <= out[7 : 4];
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ANreg[2]: semseg <= out[11: 8];
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ANreg[3]: semseg <= out[15:12];
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ANreg[4]: semseg <= out[19:16];
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ANreg[5]: semseg <= out[23:20];
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ANreg[6]: semseg <= out[27:24];
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ANreg[7]: semseg <= out[31:28];
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endcase
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case (semseg)
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4'h1: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //L
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4'h3: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110110; //?
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4'h8: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; //O
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4'hA: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; //A
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4'hC: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001000; //H
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default: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; //
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endcase
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end
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end
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endmodule
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