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89 lines
3.4 KiB
Systemverilog
89 lines
3.4 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Alexander Kharlamov
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* Email(s) : sasha_xarlamov@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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package vgachargen_pkg;
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parameter int unsigned HD = 640; // Display area
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parameter int unsigned HF = 16; // Front porch
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parameter int unsigned HR = 96; // Retrace/Sync
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parameter int unsigned HB = 48; // Back Porch
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parameter int unsigned VD = 480;
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parameter int unsigned VF = 10;
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parameter int unsigned VR = 2;
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parameter int unsigned VB = 33;
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parameter int unsigned HTOTAL = HD + HF + HR + HB;
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parameter int unsigned VTOTAL = VD + VF + VR + VB;
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parameter int unsigned VGA_MAX_H_WIDTH = $clog2(HTOTAL);
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parameter int unsigned VGA_MAX_V_WIDTH = $clog2(VTOTAL);
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parameter int unsigned BITMAP_H_PIXELS = 8;
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parameter int unsigned BITMAP_V_PIXELS = 16;
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parameter int unsigned BITMAP_H_WIDTH = $clog2(BITMAP_H_PIXELS);
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parameter int unsigned BITMAP_V_WIDTH = $clog2(BITMAP_V_PIXELS);
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parameter int unsigned CH_T_DATA_WIDTH = BITMAP_H_PIXELS * BITMAP_V_PIXELS;
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parameter int unsigned BITMAP_ADDR_WIDTH = $clog2(CH_T_DATA_WIDTH);
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parameter int unsigned CHARSET_COUNT = 256;
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parameter int unsigned CH_T_ADDR_WIDTH = $clog2(CHARSET_COUNT/2);
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parameter int unsigned CH_H_PIXELS = HD / BITMAP_H_PIXELS;
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parameter int unsigned CH_V_PIXELS = VD / BITMAP_V_PIXELS;
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parameter int unsigned CH_V_WIDTH = $clog2(CH_V_PIXELS);
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parameter int unsigned CH_H_WIDTH = $clog2(CH_H_PIXELS);
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parameter int unsigned CH_MAP_ADDR_WIDTH = CH_V_WIDTH + CH_H_WIDTH;
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parameter int unsigned CH_MAP_DATA_WIDTH = CH_T_ADDR_WIDTH + 1;
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parameter int unsigned COL_MAP_ADDR_WIDTH = CH_MAP_ADDR_WIDTH;
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typedef enum logic [23:0] {
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COL_0 = 24'h000000,
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COL_1 = 24'h0000d8,
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COL_2 = 24'h00d800,
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COL_3 = 24'h00d8d8,
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COL_4 = 24'hd80000,
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COL_5 = 24'hd800d8,
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COL_6 = 24'hd8d800,
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COL_7 = 24'hd8d8d8,
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COL_9 = 24'h0000ff,
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COL_10 = 24'h00ff00,
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COL_11 = 24'h00ffff,
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COL_12 = 24'hff0000,
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COL_13 = 24'hff00ff,
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COL_14 = 24'hffff00,
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COL_15 = 24'hffffff
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} rgb_t;
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function automatic logic [11:0] rgb2half(rgb_t rgb_i);
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return {rgb_i[23:20], rgb_i[15:12], rgb_i[7:4]};
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endfunction
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function automatic logic [11:0] color_decode(logic [3:0] color_encoded_i);
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unique case (color_encoded_i)
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4'h0 : return rgb2half(COL_0 );
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4'h1 : return rgb2half(COL_1 );
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4'h2 : return rgb2half(COL_2 );
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4'h3 : return rgb2half(COL_3 );
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4'h4 : return rgb2half(COL_4 );
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4'h5 : return rgb2half(COL_5 );
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4'h6 : return rgb2half(COL_6 );
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4'h7 : return rgb2half(COL_7 );
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4'h8 : return rgb2half(COL_0 );
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4'h9 : return rgb2half(COL_9 );
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4'ha : return rgb2half(COL_10);
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4'hb : return rgb2half(COL_11);
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4'hc : return rgb2half(COL_12);
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4'hd : return rgb2half(COL_13);
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4'he : return rgb2half(COL_14);
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4'hf : return rgb2half(COL_15);
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default: return rgb2half(COL_0 );
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endcase
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endfunction
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endpackage
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