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APS/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg
Andrei Solodovnikov 9739429d6e Синхронизация с правками публикуемого издания (#101) 
* СП. Обновление предисловия

* СП. Обновление введения

* СП. Обновление лаб

* СП. Обновление доп материалов

* СП. Введение

* СП. Введение

* СП. ЛР№4, 15

* СП. Базовые конструкции Verilog

* Update Implementation steps.md

* СП. ЛР 4,5,7,8,14

* СП. ЛР№8

* Синхронизация правок

* СП. Финал

* Исправление ссылки на рисунок

* Обновление схемы

* Синхронизация правок

* Добавление белого фона .drawio-изображениям

* ЛР2. Исправление нумерации рисунка
2025-02-12 17:53:52 +03:00

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module
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blocking_assignment
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(
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input
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</span>
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logic
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a, b
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<span style="color: rgb(0, 0, 0);">
</span>
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output
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logic
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c, d
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);
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<br/>
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<font color="#009900">
// блокирующее присваивание
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always_ff
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@(posedge clk) begin
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b = a;
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<br/>
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c = b;
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// обновленное значение b
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<span style="color: rgb(0, 0, 0);">
<br/>
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d = c;
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// обновленное значение с
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end
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<br/>
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endmodule
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module
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non
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bloc
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king_a
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ssignment
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(
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</span>
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input
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</span>
<span style="color: rgb(0, 0, 255);">
logic
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a, b
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<span style="color: rgb(0, 0, 0);">
</span>
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output
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</span>
<span style="color: rgb(0, 0, 255);">
logic
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c, d
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<span style="color: rgb(0, 0, 0);">
);
</span>
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<div style="line-height: 19px;">
<br/>
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<font color="#009900">
// неблокирующее присваивание
<br/>
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<font color="#af00db">
always_ff
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@(posedge clk) begin
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<span style="color: rgb(175, 0, 219);">
</span>
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b &lt;= a;
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<br/>
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c &lt;= b;
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// старое значение b
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<br/>
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d &lt;= c;
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// старое значение c
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end
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<br/>
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endmodule
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module nonblocking_assignment(...
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