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81 lines
2.0 KiB
Systemverilog
81 lines
2.0 KiB
Systemverilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: MIET
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// Engineer: Nikita Bulavin
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//
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// Create Date:
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// Design Name:
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// Module Name: tb_fulladder
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// Project Name: RISCV_practicum
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// Target Devices: Nexys A7-100T
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// Tool Versions:
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// Description: tb for 1-bit fulladder
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_fulladder();
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parameter TIME_OPERATION = 100;
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parameter TEST_VALUES = 8;
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wire tb_a_i;
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wire tb_b_i;
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wire tb_carry_i;
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wire tb_carry_o;
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wire tb_sum_o;
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fulladder DUT (
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.a_i(tb_a_i),
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.b_i(tb_b_i),
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.sum_o(tb_sum_o),
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.carry_i(tb_carry_i),
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.carry_o(tb_carry_o)
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);
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integer i, err_count = 0;
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reg [4:0] running_line;
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wire sum_dump;
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wire carry_o_dump;
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assign tb_a_i = running_line[4];
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assign tb_b_i = running_line[3];
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assign tb_carry_i = running_line[2];
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assign sum_dump = running_line[1];
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assign carry_o_dump = running_line[0];
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initial begin
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$display( "Start test: ");
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for ( i = 0; i < TEST_VALUES; i = i + 1 )
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begin
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running_line = line_dump[i*5+:5];
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#TIME_OPERATION;
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if( (tb_carry_o !== carry_o_dump) || (tb_sum_o !== sum_dump) ) begin
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$display("ERROR! carry_i = %b; (a)%b + (b)%b = ", tb_carry_i, tb_a_i, tb_b_i, "(carry_o)%b (sum_o)%b;", tb_carry_o, tb_sum_o, " carry_o_dump: %b, sum_dump: %b", carry_o_dump, sum_dump);
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err_count = err_count + 1'b1;
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end
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end
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$display("Number of errors: %d", err_count);
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if( !err_count ) $display("\nfulladder SUCCESS!!!\n");
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$finish();
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end
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reg [5*8-1:0] line_dump = {
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5'b00000,
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5'b10010,
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5'b01010,
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5'b11001,
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5'b00110,
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5'b10101,
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5'b01101,
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5'b11111};
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endmodule
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