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ЛР2. Исправление подключения модуля в nexys_alu

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Andrei Solodovnikov
2024-09-09 14:35:29 +03:00
committed by GitHub
parent 8396bb51ab
commit ffec97f5ac
1 changed files with 1 additions and 1 deletions
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2
Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv
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@@ -45,7 +45,7 @@ module nexys_alu(
logic [31:0] result;
logic flag;
alu_riscv alu_riscv (
alu alu_riscv (
.alu_op_i (operator),
.a_i (operand_a),
.b_i (operand_b),