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Ref(03/board/nexys_rf_riscv):Уд-ие reg wd

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Тк не нужно и усложняет схему
This commit is contained in:
alexkharl
2024-02-27 16:33:23 +03:00
parent e5f26df2ba
commit fe87b1a9fe
1 changed files with 2 additions and 22 deletions
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24
Labs/03. Register file and memory/board files/nexys_rf_riscv.sv
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@@ -131,28 +131,8 @@ module nexys_rf_riscv(
assign ra1 = ra1_ff;
assign ra2 = ra2_ff;
logic [15:0] wd_ff;
logic wd_en;
assign wd_en = btnr_i;
logic [15:0] wd_next;
assign wd_next = sw_i;
always_ff @(posedge clk_i or negedge arstn_i) begin
if (!arstn_i) begin
wd_ff <= '0;
end else if (wd_en) begin
wd_ff <= wd_next;
end
end
assign wd = {16'b0, wd_ff};
logic we_ff;
logic we_next;
assign we_next = wd_en;
always_ff @(posedge clk_i or negedge arstn_i) begin
if (!arstn_i) we_ff <= 1'b0;
else we_ff <= we_next;
end
assign we = we_ff;
assign wd = {16'b0, sw_i};
assign we = btnr_i;
assign {ca_o, cb_o, cc_o, cd_o, ce_o, cf_o, cg_o} = semseg;
assign dp_o = 1'b1;