From fe87b1a9fe0d3d14d5cacaba92e647b5a8753271 Mon Sep 17 00:00:00 2001 From: alexkharl Date: Tue, 27 Feb 2024 16:33:23 +0300 Subject: [PATCH] =?UTF-8?q?Ref(03/board/nexys=5Frf=5Friscv):=D0=A3=D0=B4-?= =?UTF-8?q?=D0=B8=D0=B5=20reg=20wd?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Тк не нужно и усложняет схему --- .../board files/nexys_rf_riscv.sv | 24 ++----------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv b/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv index 675804a..02b494c 100644 --- a/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv +++ b/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv @@ -131,28 +131,8 @@ module nexys_rf_riscv( assign ra1 = ra1_ff; assign ra2 = ra2_ff; - logic [15:0] wd_ff; - logic wd_en; - assign wd_en = btnr_i; - logic [15:0] wd_next; - assign wd_next = sw_i; - always_ff @(posedge clk_i or negedge arstn_i) begin - if (!arstn_i) begin - wd_ff <= '0; - end else if (wd_en) begin - wd_ff <= wd_next; - end - end - assign wd = {16'b0, wd_ff}; - - logic we_ff; - logic we_next; - assign we_next = wd_en; - always_ff @(posedge clk_i or negedge arstn_i) begin - if (!arstn_i) we_ff <= 1'b0; - else we_ff <= we_next; - end - assign we = we_ff; + assign wd = {16'b0, sw_i}; + assign we = btnr_i; assign {ca_o, cb_o, cc_o, cd_o, ce_o, cf_o, cg_o} = semseg; assign dp_o = 1'b1;