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ЛР6. Обновление программы

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This commit is contained in:
Andrei Solodovnikov
2023-09-10 20:56:53 +03:00
parent 182a848b43
commit f92ceee371
3 changed files with 77 additions and 116 deletions
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60
Labs/06. Datapath/README.md
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@@ -78,20 +78,27 @@
0C: and x4, x1, x2
10: sub x5, x4, x3
14: mul x6, x3, x4 // неподдерживаемая инструкция
18: jal x15, 0x00034 // прыжок на адрес 0x4C
18: jal x15, 0x00050 // прыжок на адрес 0x68
1C: jalr x15, 0x0(x6)
20: slli x7, x5, 31
24: srai x8, x7, 1
28: srli x9, x8, 29
2C: sw x1, 0x0(x4)
30: lw x10, 0x0(x4)
34: lui x11, 0xFFF80
38: auipc x12, 0x00004
3C: bne x3, x4, 0x08 // перескок через
40: // нелегальную нулевую инструкцию
44: jal x13, 0x00004
48: jalr x14, 0x0(x13)
4C: jalr x15, 0x4(x15)
2C: lui x10, 0xfadec
30: add x10, x10,-1346
34: sw x10, 0x0(x4)
38: sh x10, 0x6(x4)
3C: sb x10, 0xb(x4)
40: lw x11, 0x0(x4)
44: lh x12, 0x0(x4)
48: lb x13, 0x0(x4)
4С: lhu x14, 0x0(x4)
50: lbu x15, 0x0(x4)
54: auipc x16, 0x00004
58: bne x3, x4, 0x08 // перескок через
5С: // нелегальную нулевую инструкцию
60: jal x17, 0x00004
64: jalr x14, 0x0(x17)
68: jalr x18, 0x4(x15)
```
Теперь в соответствии с кодировкой инструкций переведем программу в машинные коды:
@@ -99,24 +106,31 @@
```text
00: 011101011100 00000 000 00001 0010011
04: 100010100111 00000 000 00010 0010011
08: 0000000 00001 00010 000 00011 0110011
0C: 0000000 00001 00010 111 00100 0110011
08: 0000000 00010 00001 000 00011 0110011
0C: 0000000 00010 00001 111 00100 0110011
10: 0100000 00011 00100 000 00101 0110011
14: 0000001 00011 00100 000 00110 0110011
18: 00000011010000000000 01111 1101111
14: 0000001 00100 00011 000 00110 0110011
18: 00000101000000000000 01111 1101111
1C: 000000000000 00110 000 01111 1100111
20: 0000000 11111 00101 001 00111 0010011
24: 0100000 00001 00111 101 01000 0010011
28: 0000000 11101 01000 101 01001 0010011
2C: 0000000 00001 00100 010 00000 0100011
30: 000000000000 00100 010 01010 0000011
34: 11111111111110000000 01011 0110111
38: 00000000000000000100 01100 0010111
3C: 0000000 00011 00100 001 01000 1100011
40: 00000000 00000000 00000000 00000000
44: 00000000010000000000 01101 1101111
48: 000000000000 01101 000 01110 1100111
4C: 000000000100 01111 000 01111 1100111
2C: 11011110101011011100 01010 0110111
30: 111010101111 01010 000 01010 0010011
34: 0000000 01010 00100 010 00000 0100011
38: 0000000 01010 00100 001 00110 0100011
3C: 0000000 01010 00100 000 01011 0100011
40: 000000000000 00100 010 01011 0000011
44: 000000000000 00100 001 01100 0000011
48: 000000000000 00100 000 01101 0000011
4C: 000000000000 00100 101 01110 0000011
50: 000000000000 00100 100 11101 0000011
54: 00000000000000000100 10000 0010111
58: 0000000 00011 00100 001 01000 1100011
5C: 00000000 00000000 00000000 00000000
60: 00000000010000000000 10001 1101111
64: 000000000000 10001 000 01110 1100111
68: 000000000100 01111 000 10010 1100111
```
Данная программа, представленная в шестнадцатиричном формате находится в файле [program.txt](program.txt).

107
Labs/06. Datapath/program.txt
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@@ -1,80 +1,27 @@
93
00
c0
75
13
01
70
8a
b3
01
11
00
33
72
11
00
b3
02
32
40
33
83
41
02
ef
07
40
03
e7
07
03
00
93
93
f2
01
13
d4
13
40
93
54
d4
01
23
20
12
00
03
25
02
00
b7
05
f8
ff
17
46
00
00
63
94
41
00
00
00
00
00
ef
06
40
00
67
87
06
00
e7
87
47
00
75C00093
8A700113
002081B3
0020F233
403202B3
02418333
050007EF
000307E7
01F29393
4013D413
01D45493
fadec537
abe50513
00A22023
00A21323
00A205A3
00022583
00021603
00020683
00025703
00024783
00004817
00321463
00000000
004008EF
00088767
00478967

26
Labs/06. Datapath/tb_riscv_unit.sv
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@@ -2,20 +2,20 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
//
// Create Date:
// Design Name:
//
// Create Date:
// Design Name:
// Module Name: tb_riscv_unit
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Tool Versions:
// Description: tb for datapath
//
// Dependencies:
//
// Revision:
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
@@ -36,16 +36,16 @@ module tb_riscv_unit();
rst = 1;
#20;
rst = 0;
#500;
#800;
$display("\n The test is over \n See the internal signals of the module on the waveform \n");
$finish;
end
stall: assert property (
stall_seq: assert property (
@(posedge clk)
disable iff ( rst )
(top.mem_req) |-> (top.stall) |-> ##1 (!top.stall & top.mem_req)
disable iff ( !unit.mem_req )
$past(unit.mem_req) |-> !$stable(unit.stall)
)else $error("\n================================================\nThe realisation of the STALL signal is INCORRECT\n================================================\n");
endmodule