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ЛР8. Обновление имени готового модуля

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Andrei Solodovnikov
2024-11-23 17:18:11 +03:00
parent 001fe2d91e
commit f6815409e2
1 changed files with 1 additions and 1 deletions
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Labs/Made-up modules/lab_08.lsu.sv
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@@ -8,7 +8,7 @@
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module riscv_lsu(
module lsu(
input logic clk_i,
input logic rst_i,
input logic core_req_i,