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95
Labs/09. Peripheral units/PS2Receiver.v
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95
Labs/09. Peripheral units/PS2Receiver.v
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`timescale 1ns / 1ps
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module PS2Receiver(
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input clk,
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input kclk,
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input kdata,
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output reg [15:0] keycodeout,
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output keycode_valid
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);
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reg flag;
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reg [3:0] flag_shift;
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wire kclkf, kdataf;
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reg [3:0]cnt;
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assign keycode_valid = flag_shift[0] && !flag_shift[2];
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initial begin //for tb
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cnt = 0;
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keycodeout = 0;
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flag_shift = 0;
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flag = 0;
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end
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debouncer debounce(
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.clk(clk),
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.I0(kclk),
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.I1(kdata),
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.O0(kclkf),
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.O1(kdataf)
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);
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always@(posedge clk) begin
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flag_shift <= (flag_shift << 1) + flag;
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end
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always@(negedge(kclkf))begin
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case(cnt)
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0:if(keycodeout != 16'hE000)keycodeout <= 0;//Start bit
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1:keycodeout[0]<=kdataf;
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2:keycodeout[1]<=kdataf;
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3:keycodeout[2]<=kdataf;
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4:keycodeout[3]<=kdataf;
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5:keycodeout[4]<=kdataf;
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6:keycodeout[5]<=kdataf;
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7:keycodeout[6]<=kdataf;
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8:keycodeout[7]<=kdataf;
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//TODO ADD PARITY CHECK
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9:begin
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flag<=1'b1;
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if(keycodeout[7:0] == 8'hE0) begin
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keycodeout <= {keycodeout[7:0], 8'd0};
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end
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end
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10:flag<=1'b0;
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default: cnt <= 0;
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endcase
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if(cnt<=9) cnt<=cnt+1;
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else if(cnt==10) cnt<=0;
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end
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endmodule
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module debouncer(
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input clk,
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input I0,
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input I1,
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output reg O0,
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output reg O1
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);
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reg [4:0]cnt0, cnt1;
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reg Iv0=0,Iv1=0;
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reg out0, out1;
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always@(posedge(clk))begin
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if (I0==Iv0)begin
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if (cnt0==19)O0<=I0;
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else cnt0<=cnt0+1;
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end
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else begin
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cnt0<="00000";
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Iv0<=I0;
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end
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if (I1==Iv1)begin
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if (cnt1==19)O1<=I1;
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else cnt1<=cnt1+1;
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end
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else begin
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cnt1<="00000";
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Iv1<=I1;
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end
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end
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endmodule
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