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This commit is contained in:
Andrei Solodovnikov
148
Labs/06. Datapath/board files/nexys_riscv_unit.sv
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148
Labs/06. Datapath/board files/nexys_riscv_unit.sv
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`timescale 1ns / 1ps
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module nexys_riscv_unit(
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input CLK100,
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input resetn,
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input BTND,
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output CA, CB, CC, CD, CE, CF, CG,
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output [7:0] AN
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);
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riscv_unit unit(
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.clk_i(btn),
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.rst_i(!resetn)
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);
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wire [31:0] instr_addr;
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wire [31:0] instr;
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reg btn;
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assign instr_addr = unit.instr_addr;
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assign instr = unit.instr;
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localparam pwm = 1000;
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reg [9:0] counter;
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reg [7:0] semseg;
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reg [7:0] ANreg;
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reg CAr, CBr, CCr, CDr, CEr, CFr, CGr;
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assign AN[7:0] = ANreg[7:0];
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assign {CA, CB, CC, CD, CE, CF, CG} = {CAr, CBr, CCr, CDr, CEr, CFr, CGr};
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always @(posedge CLK100) begin
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if (!resetn) begin
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counter <= 'b0;
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ANreg[7:0] <= 8'b11111111;
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{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111;
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btn <= BTND;
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end
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else begin
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btn <= BTND;
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if (counter < pwm) counter = counter + 'b1;
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else begin
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counter = 'b0;
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ANreg[1] <= ANreg[0];
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ANreg[2] <= ANreg[1];
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ANreg[3] <= ANreg[2];
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ANreg[4] <= ANreg[3];
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ANreg[5] <= ANreg[4];
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ANreg[6] <= ANreg[5];
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ANreg[7] <= ANreg[6];
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ANreg[0] <= !(ANreg[6:0] == 7'b1111111);
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end
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if(|(~ANreg[5:4])) begin
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case (1'b0)
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ANreg[4]: semseg <= instr_addr[3:0];
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ANreg[5]: semseg <= instr_addr[7:4];
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endcase
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case (semseg)
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4'h0: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001;
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4'h1: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001111;
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4'h2: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0010010;
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4'h3: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000110;
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4'h4: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001100;
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4'h5: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100100;
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4'h6: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100000;
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4'h7: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001111;
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4'h8: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000000;
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4'h9: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000100;
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4'hA: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000;
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4'hB: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1100000;
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4'hC: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110001;
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4'hD: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000010;
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4'hE: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110000;
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4'hF: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0111000;
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default: {CAr,CBr,CCr,CDr, CEr, CFr, CGr} <= 7'b0111111;
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endcase
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end else begin
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case (1'b0)
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ANreg[7]: begin
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{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0011000;
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end
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ANreg[6]: begin
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{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110001;
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end
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ANreg[3]: begin
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case(instr[6:2])
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5'b01101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; //LUI -
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5'b00101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; //AUIP A
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5'b11011:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; //JAL -
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5'b11001:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000111; //JALR J
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5'b11000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1100000; //brch b
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5'b00000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //LOAd L
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5'b01000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100100; //STOr S
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5'b00100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; //OPIM O
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5'b01100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; //OP -
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default: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111001; //ILLE I
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endcase
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end
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ANreg[2]: begin
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case(instr[6:2])
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5'b01101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //LUI L
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5'b00101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000001; //AUIP U
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5'b11011:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000111; //JAL J
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5'b11001:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; //JALR A
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5'b11000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111010; //brch r
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5'b00000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; //LOAd O
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5'b01000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110000; //StOr t
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5'b00100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0011000; //OPIM P
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5'b01100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; //OP -
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default: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //ILLE L
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endcase
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end
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ANreg[1]: begin
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case(instr[6:2])
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5'b01101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000001; //LUI U
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5'b00101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111001; //AUIP I
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5'b11011:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; //JAL A
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5'b11001:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //JALR L
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5'b11000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110010; //brch c
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5'b00000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; //LOAd A
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5'b01000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; //STOr O
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5'b00100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111001; //OPIM I
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5'b01100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; //OP O
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default: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //ILLE L
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endcase
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end
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ANreg[0]: begin
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case(instr[6:2])
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5'b01101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111001; //LUI I
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5'b00101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0011000; //AUIP P
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5'b11011:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //JAL L
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5'b11001:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111010; //JALr r
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5'b11000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1101000; //brch h
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5'b00000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000010; //LOAd d
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5'b01000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111010; //STOr r
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5'b00100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0101010; //OPIM M
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5'b01100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0011000; //OP P
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default: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110000; //ILLE E
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endcase
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end
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endcase
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end
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end
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end
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endmodule
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