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English version draft
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Andrei Solodovnikov
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# Summary
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[Порядок выполнения лабораторных работ для групп](index.md)
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[Предисловие](Intro.md)
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[Lab schedule by group](index.md)
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[Preface](Intro.md)
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---
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# Введение
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# Introduction
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- [О данном разделе](Introduction/README.md)
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- [Что такое Язык Описания Аппаратуры](Introduction/What%20is%20HDL.md)
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- [Как работает ПЛИС](Introduction/How%20FPGA%20works.md)
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- [Последовательностная логика](Introduction/Sequential%20logic.md)
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- [Этапы реализации проекта в ПЛИС](Introduction/Implementation%20steps.md)
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- [About this section](Introduction/README.md)
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- [What is a Hardware Description Language](Introduction/What%20is%20HDL.md)
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- [How FPGAs work](Introduction/How%20FPGA%20works.md)
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- [Sequential logic](Introduction/Sequential%20logic.md)
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- [FPGA implementation steps](Introduction/Implementation%20steps.md)
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---
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# Лабораторные работы
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# Laboratory works
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- [Лабораторная №1. Сумматор](Labs/01.%20Adder/README.md)
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- [Лабораторная №2. АЛУ](Labs/02.%20Arithmetic-logic%20unit/README.md)
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- [Лабораторная №3. Регистровый файл и внешняя память](Labs/03.%20Register%20file%20and%20memory/README.md)
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- [Лабораторная №4. Простейшее программируемое устройство](Labs/04.%20Primitive%20programmable%20device/README.md)
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- [Написание программы под процессор CYBERcobra](Labs/04.%20Primitive%20programmable%20device/Индивидуальное%20задание/README.md)
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- [Лабораторная №5. Декодер инструкций](Labs/05.%20Main%20decoder/README.md)
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- [Лабораторная №6. Основная память](Labs/06.%20Main%20memory/README.md)
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- [Лабораторная №7. Тракт данных](Labs/07.%20Datapath/README.md)
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- [Лабораторная №8. Блок загрузки и сохранения](Labs/08.%20Load-store%20unit/README.md)
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- [Лабораторная №9. Интеграция LSU](Labs/09.%20LSU%20Integration/README.md)
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- [Лабораторная №10. Подсистема прерывания](Labs/10.%20Interrupt%20subsystem/README.md)
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- [Лабораторная №11. Интеграция подсистемы прерывания](Labs/11.%20Interrupt%20integration/README.md)
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- [Лабораторная №12. Блок приоритетных прерываний](Labs/12.%20Daisy%20chain/README.md)
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- [Лабораторная №13. Периферийные устройства](Labs/13.%20Peripheral%20units/README.md)
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- [Лабораторная №14. Программирование](Labs/14.%20Programming/README.md)
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- [Лабораторная №15. Программатор](Labs/15.%20Programming%20device/README.md)
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- [Лабораторная №16. Оценка производительности](Labs/16.%20Coremark/README.md)
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- [Lab 1. Adder](Labs/01.%20Adder/README.md)
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- [Lab 2. ALU](Labs/02.%20Arithmetic-logic%20unit/README.md)
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- [Lab 3. Register file and external memory](Labs/03.%20Regiter%20file%20and%20memory/README.md)
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- [Lab 4. Primitive programmable device](Labs/04.%20Primtive%20programmable%20device/README.md)
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- [Writng a program for the CYBERcobra processor](Labs/04.%20Primtive%20programmable%20device/Индивидуальное%20задание/README.md)
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- [Lab 5. Instruction decoder](Labs/05.%20Main%20decoder/README.md)
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- [Lab 6. Main memory](Labs/06.%20Main%20memory/README.md)
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- [Lab 7. Datapath](Labs/07.%20Datapath/README.md)
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- [Lab 8. Load-store unit](Labs/08.%20Load-store%20unit/README.md)
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- [Lab 9. LSU integration](Labs/09.%20LSU%20Integration/README.md)
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- [Lab 10. Interrupt subsystem](Labs/10.%20Interrupt%20subsystem/README.md)
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- [Lab 11. Interrupt subsystem integration](Labs/11.%20Interrupt%20integration/README.md)
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- [Lab 12. Priority interrupt unit (Daisy chain)](Labs/12.%20Daisy%20chain/README.md)
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- [Lab 13. Peripheral devices](Labs/13.%20Peripheral%20units/README.md)
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- [Lab 14. Programming](Labs/14.%20Programming/README.md)
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- [Lab 15. Programmer device](Labs/15.%20Programming%20device/README.md)
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- [Lab 16. Performance evaluation](Labs/16.%20Coremark/README.md)
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---
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# Базовые конструкции SystemVerilog
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# Basic SystemVerilog constructs
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- [Описание раздела](Basic%20Verilog%20structures/README.md)
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- [Модули](Basic%20Verilog%20structures/Modules.md)
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- [Мультиплексоры](Basic%20Verilog%20structures/Multiplexors.md)
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- [Регистры](Basic%20Verilog%20structures/Registers.md)
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- [Конкатенация](Basic%20Verilog%20structures/Concatenation.md)
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- [Защелки](Basic%20Verilog%20structures/Latches.md)
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- [О различиях между блокирующими и неблокирующими присваиваниями](Basic%20Verilog%20structures/Assignments.md)
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- [Контроллеры](Basic%20Verilog%20structures/Controllers.md)
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- [Section overview](Basic%20Verilog%20structures/README.md)
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- [Modules](Basic%20Verilog%20structures/Modules.md)
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- [Multiplexers](Basic%20Verilog%20structures/Multiplexors.md)
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- [Registers](Basic%20Verilog%20structures/Registers.md)
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- [Concatenation](Basic%20Verilog%20structures/Concatenation.md)
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- [Latches](Basic%20Verilog%20structures/Latches.md)
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- [Blocking vs non-blocking assignments](Basic%20Verilog%20structures/Assignments.md)
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- [Controllers](Basic%20Verilog%20structures/Controllers.md)
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---
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# Основы Vivado
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# Vivado Basics
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1. [Создание проекта в Vivado](Vivado%20Basics/01.%20New%20project.md)
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2. [Навигатор по маршруту проектирования](Vivado%20Basics/02.%20Flow%20Navigator.md)
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3. [Менеджер проекта](Vivado%20Basics/03.%20Project%20manager.md)
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4. [Симуляция](Vivado%20Basics/04.%20Simulation.md)
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5. [Руководство по поиску функциональных ошибок](Vivado%20Basics/05.%20Bug%20hunting.md)
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6. [Анализ RTL](Vivado%20Basics/06.%20RTL%20Analysis.md)
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7. [Руководство по прошивке ПЛИС](Vivado%20Basics/07.%20Program%20and%20debug.md)
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8. [Руководство по работе с ошибками обработки кода](Vivado%20Basics/08.%20Code%20processing%20errors.md)
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1. [Creating a project in Vivado](Vivado%20Basics/01.%20New%20project.md)
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2. [Flow Navigator](Vivado%20Basics/02.%20Flow%20Navigator.md)
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3. [Project Manager](Vivado%20Basics/03.%20Project%20manager.md)
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4. [Simulation](Vivado%20Basics/04.%20Simulation.md)
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5. [Functional bug hunting guide](Vivado%20Basics/05.%20Bug%20hunting.md)
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6. [RTL Analysis](Vivado%20Basics/06.%20RTL%20Analysis.md)
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7. [FPGA programming guide](Vivado%20Basics/07.%20Program%20and%20debug.md)
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8. [Code processing errors guide](Vivado%20Basics/08.%20Code%20processing%20errors.md)
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# Дополнительные материалы
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# Additional materials
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- [RV32I - Стандартный набор целочисленных инструкций RISC-V](Other/rv32i.md)
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- [О регистрах контроля и статуса](Other/CSR.md)
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- [Список типичных ошибок при работе с Vivado и SystemVerilog](Other/FAQ.md)
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- [RV32I — RISC-V Base Integer Instruction Set](Other/rv32i.md)
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- [Control and Status Registers (CSR)](Other/CSR.md)
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- [Common Vivado & SystemVerilog pitfalls](Other/FAQ.md)
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