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Исправление подключения сумматора в nexys_adder

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This commit is contained in:
Andrei Solodovnikov
2023-09-18 11:10:28 +03:00
committed by GitHub
parent 16b837078e
commit e50170db94
1 changed files with 6 additions and 6 deletions
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12
Labs/01. Adder/board files/nexys_adder.sv
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@@ -30,12 +30,12 @@ reg [15:0] LEDr;
fulladder32 DUT fulladder32 DUT
( (
.A (A), .a_i (A),
.B (B), .b_i (B),
.Pin (Pin), .carry_i (Pin),
.S (S), .sum_o (S),
.Pout (Pout) .carry_o (Pout)
); );
assign B = {24'b0,SW[7:0]}; assign B = {24'b0,SW[7:0]};
@@ -127,4 +127,4 @@ always @(posedge CLK100) begin
end end
end end
endmodule endmodule