diff --git a/Labs/01. Adder/board files/nexys_adder.sv b/Labs/01. Adder/board files/nexys_adder.sv
index f4c69ac..0847b5d 100644
--- a/Labs/01. Adder/board files/nexys_adder.sv	
+++ b/Labs/01. Adder/board files/nexys_adder.sv	
@@ -30,12 +30,12 @@ reg [15:0] LEDr;
 
 fulladder32 DUT
 (
-  .A    (A),
-  .B    (B),
-  .Pin  (Pin),
+  .a_i     (A),
+  .b_i     (B),
+  .carry_i (Pin),
   
-  .S    (S),
-  .Pout (Pout)
+  .sum_o   (S),
+  .carry_o (Pout)
 );
 
 assign B = {24'b0,SW[7:0]};
@@ -127,4 +127,4 @@ always @(posedge CLK100) begin
     end
 end
 
-endmodule
\ No newline at end of file
+endmodule