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Feat(labs/03/board):Переписывание топа
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alexkharl
@@ -9,140 +9,156 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module nexys_rf_riscv(
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input CLK100,
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input resetn,
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input BTND, BTNU, BTNL, BTNR, BTNC,
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input [15:0] SW,
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output [15:0] LED,
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output CA, CB, CC, CD, CE, CF, CG, DP,
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output [7:0] AN,
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output LED16_B, LED16_G, LED16_R, LED17_B, LED17_G, LED17_R
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);
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wire [31:0] WD3;
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wire WE;
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wire [31:0] RD1;
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wire [31:0] RD2;
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localparam pwm = 1000;
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reg [9:0] counter;
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reg [3:0] semseg;
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reg [7:0] ANreg;
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reg CAr, CBr, CCr, CDr, CEr, CFr, CGr, DPr;
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reg [15:0] LEDr;
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reg [4:0] a1;
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reg [4:0] a2;
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reg [4:0] a3;
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reg [31:0] rd1;
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reg [31:0] rd2;
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rf_riscv DUT
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(
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.clk_i (CLK100 ),
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.read_addr1_i (a1 ),
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.read_addr2_i (a2 ),
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.write_addr_i (a3 ),
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.write_data_i (WD3 ),
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.write_enable_i (WE ),
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.read_data1_o (RD1 ),
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.read_data2_o (RD2 )
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input logic clk_i,
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input logic arstn_i,
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input logic [15:0] sw_i,
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input logic btnd_i,
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input logic btnr_i,
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output logic [15:0] led_o,
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output logic ca_o,
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output logic cb_o,
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output logic cc_o,
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output logic cd_o,
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output logic ce_o,
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output logic cf_o,
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output logic cg_o,
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output logic dp_o,
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output logic [ 7:0] an_o
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);
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assign LED = {1'b0, a1, a2, a3};
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assign AN[7:0] = ANreg[7:0];
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assign {CA, CB, CC, CD, CE, CF, CG, DP} = {CAr, CBr, CCr, CDr, CEr, CFr, CGr, DPr};
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assign LED16_G = BTNC | BTNR;
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assign LED17_G = BTNL | BTNR;
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assign {LED16_R, LED17_R} = {2{BTND}};
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assign {LED16_B, LED17_B} = {2{BTNU}};
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logic [ 4:0] ra1;
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logic [ 4:0] ra2;
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logic [ 4:0] wa;
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logic [31:0] wd;
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logic we;
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logic [7:0][3:0] rd1;
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logic [7:0][3:0] rd2;
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assign WD3 = 32'b0 | SW[15:0];
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assign WE = BTND;
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rf_riscv rf_riscv (
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.clk_i (clk_i),
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.read_addr1_i (ra1 ),
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.read_addr2_i (ra2 ),
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.write_addr_i (wa ),
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.write_data_i (wd ),
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.write_enable_i (we ),
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.read_data1_o (rd1 ),
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.read_data2_o (rd2 )
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);
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function automatic logic [6:0] hex2semseg(input logic [3:0] hex);
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unique case (hex)
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4'h0: return 7'b0000001;
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4'h1: return 7'b1001111;
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4'h2: return 7'b0010010;
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4'h3: return 7'b0000110;
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4'h4: return 7'b1001100;
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4'h5: return 7'b0100100;
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4'h6: return 7'b0100000;
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4'h7: return 7'b0001111;
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4'h8: return 7'b0000000;
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4'h9: return 7'b0000100;
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4'hA: return 7'b0001000;
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4'hB: return 7'b1100000;
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4'hC: return 7'b0110001;
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4'hD: return 7'b1000010;
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4'hE: return 7'b0110000;
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4'hF: return 7'b0111000;
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endcase
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endfunction
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always @(posedge CLK100) begin
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if (!resetn) begin
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counter <= 'b0;
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ANreg[7:0] <= 8'b11111111;
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{CAr, CBr, CCr, CDr, CEr, CFr, CGr, DPr} <= 8'b11111111;
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{a1, a2, a3} <= 'b0;
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{rd1, rd2} <= 'b0;
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end
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else begin
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if (counter < pwm) counter = counter + 'b1;
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else begin
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counter = 'b0;
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ANreg[1] <= ANreg[0];
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ANreg[2] <= ANreg[1];
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ANreg[3] <= ANreg[2];
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ANreg[4] <= ANreg[3];
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ANreg[5] <= ANreg[4];
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ANreg[6] <= ANreg[5];
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ANreg[7] <= ANreg[6];
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ANreg[0] <= !(ANreg[6:0] == 7'b1111111);
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end
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a1 <= BTNL? SW[4:0]: a1;
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a2 <= BTNC? SW[4:0]: a2;
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a3 <= BTNR? SW[4:0]: a3;
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rd1 <= BTNU? RD1: rd1;
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rd2 <= BTNU? RD2: rd2;
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case (1'b0)
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ANreg[0]: begin
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semseg <= (rd2) % 5'h10;
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//DPr <= 1'b1;
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end
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ANreg[1]: begin
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semseg <= (rd2 / 'h10) % 5'h10;
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//DPr <= 1'b1;
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end
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ANreg[2]: begin
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semseg <= (rd2 / 'h100) % 5'h10;
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//DPr <= 1'b1;
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end
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ANreg[3]: begin
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semseg <= (rd2 / 'h1000) % 5'h10;
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//DPr <= 1'b1;
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end
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ANreg[4]: begin
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semseg <= (rd1) % 5'h10;
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//DPr <= 1'b1;
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end
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ANreg[5]: begin
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semseg <= (rd1 / 'h10) % 5'h10;
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//DPr <= 1'b1;
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end
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ANreg[6]: begin
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semseg <= (rd1 / 'h100) % 5'h10;
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//DPr <= 1'b1;
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end
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ANreg[7]: begin
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semseg <= (rd1 / 'h1000) % 5'h10;
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//DPr <= 1'b1;
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end
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endcase
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case (semseg)
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4'h0: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001;
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4'h1: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001111;
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4'h2: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0010010;
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4'h3: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000110;
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4'h4: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001100;
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4'h5: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100100;
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4'h6: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100000;
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4'h7: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001111;
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4'h8: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000000;
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4'h9: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000100;
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4'hA: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000;
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4'hB: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1100000;
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4'hC: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110001;
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4'hD: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000010;
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4'hE: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110000;
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4'hF: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0111000;
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default: {CAr,CBr,CCr,CDr, CEr, CFr, CGr} <= 7'b0111111;
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endcase
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end
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localparam int COUNTER_WIDTH = 10;
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logic [COUNTER_WIDTH-1:0] counter_next;
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logic [COUNTER_WIDTH-1:0] counter_ff;
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assign counter_next = counter_ff + COUNTER_WIDTH'('b1);
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (!arstn_i) counter_ff <= '0;
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else counter_ff <= counter_next;
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end
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logic [7:0] an_ff;
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logic [7:0] an_next;
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logic an_en;
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assign an_next = {an_ff[$left(an_ff)-1:0], an_ff[$left(an_ff)]};
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assign an_en = ~|counter_ff;
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (!arstn_i) an_ff <= ~8'b1;
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else if (an_en) an_ff <= an_next;
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end
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localparam bit [6:0] BLANK = 7'b1111111;
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logic [6:0] semseg;
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always_comb begin
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semseg = BLANK;
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unique case (1'b0)
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an_ff[0]: semseg = hex2semseg(rd2[0]);
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an_ff[1]: semseg = hex2semseg(rd2[1]);
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an_ff[2]: semseg = hex2semseg(rd2[2]);
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an_ff[3]: semseg = hex2semseg(rd2[3]);
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an_ff[4]: semseg = hex2semseg(rd1[0]);
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an_ff[5]: semseg = hex2semseg(rd1[1]);
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an_ff[6]: semseg = hex2semseg(rd1[2]);
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an_ff[7]: semseg = hex2semseg(rd1[3]);
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endcase
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end
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logic [2:0][4:0] addresses_next;
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assign addresses_next = sw_i[14:0];
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logic [4:0] wa_ff;
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logic [4:0] ra1_ff;
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logic [4:0] ra2_ff;
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logic [4:0] wa_next;
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assign wa_next = addresses_next[0];
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logic [4:0] ra1_next;
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assign ra1_next = addresses_next[2];
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logic [4:0] ra2_next;
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assign ra2_next = addresses_next[1];
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logic addresses_en;
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assign addresses_en = btnr_i;
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (!arstn_i) begin
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wa_ff <= '0;
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ra1_ff <= '0;
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ra2_ff <= '0;
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end else if (addresses_en) begin
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wa_ff <= wa_next;
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ra1_ff <= ra1_next;
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ra2_ff <= ra2_next;
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end
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end
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assign wa = wa_ff;
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assign ra1 = ra1_ff;
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assign ra2 = ra2_ff;
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logic [15:0] wd_ff;
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logic wd_en;
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assign wd_en = btnd_i;
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logic [15:0] wd_next;
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assign wd_next = sw_i;
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (!arstn_i) begin
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wd_ff <= '0;
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end else if (wd_en) begin
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wd_ff <= wd_next;
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end
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end
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assign wd = {16'b0, wd_ff};
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logic we_ff;
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logic we_next;
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assign we_next = wd_en ? 1'b1 : 1'b0;
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (!arstn_i) we_ff <= 1'b0;
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else we_ff <= we_next;
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end
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assign we = we_ff;
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assign {ca_o, cb_o, cc_o, cd_o, ce_o, cf_o, cg_o} = semseg;
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assign dp_o = 1'b1;
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assign led_o = {1'b0, ra1, ra2, wa};;
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assign an_o = an_ff;
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endmodule
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