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Добавление кредитов к авторам тб

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This commit is contained in:
Andrei Solodovnikov
2024-02-04 11:13:09 +03:00
parent 45585ff9c4
commit a5715486c2
5 changed files with 55 additions and 0 deletions
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11
Labs/12. Daisy chain/tb_daisy_chain.sv
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//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Solodovnikov Andrei
// Module Name: tb_daisy_chain
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for daisy chain
//
//////////////////////////////////////////////////////////////////////////////////
module tb_daisy_chain(); module tb_daisy_chain();
logic clk_i, rst_i, ready_i, irq_ret_i; logic clk_i, rst_i, ready_i, irq_ret_i;

11
Labs/15. Programming device/tb_bluster.sv
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//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Solodovnikov Andrei
// Module Name: tb_blaster
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for programming device
//
//////////////////////////////////////////////////////////////////////////////////
module tb_blaster(); module tb_blaster();
logic clk_i; logic clk_i;

11
Labs/15. Programming device/tb_top_asic.sv
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//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Solodovnikov Andrei
// Module Name: tb_top_asic
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for top level entity
//
//////////////////////////////////////////////////////////////////////////////////
module tb_top_asic(); module tb_top_asic();
logic clk10mhz_i; logic clk10mhz_i;

11
Labs/16. Coremark/tb_coremark.sv
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//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Solodovnikov Andrei
// Module Name: tb_coremark
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for running Coremark
//
//////////////////////////////////////////////////////////////////////////////////
module tb_coremark(); module tb_coremark();
logic clk10mhz_i; logic clk10mhz_i;

11
Labs/16. Coremark/tb_timer.sv
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//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Solodovnikov Andrei
// Module Name: tb_timer
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for timer
//
//////////////////////////////////////////////////////////////////////////////////
module tb_timer(); module tb_timer();
logic clk_i; logic clk_i;