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Ref(01_Adder):Улучш-ие логирования

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alexkharl
2024-02-07 16:39:31 +03:00
parent 33c8dda06c
commit 92147fa303
3 changed files with 31 additions and 30 deletions
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12
Labs/01. Adder/tb_fulladder.sv
View File

@@ -9,9 +9,10 @@
//////////////////////////////////////////////////////////////////////////////////
module tb_fulladder();
parameter TIME_OPERATION = 100;
parameter TEST_VALUES = 8;
timeunit 1ns;
timeprecision 1ps;
parameter TIME_OPERATION = 100;
parameter TEST_VALUES = 8;
wire tb_a_i;
wire tb_b_i;
@@ -37,13 +38,16 @@ parameter TEST_VALUES = 8;
assign tb_carry_i = running_line[2];
initial begin
$timeformat(-9, 2, " ns");
$display("START simulation of 1-bit fulladder.");
$display("You should run simmulation until the message 'FINISH simulation' appears in the log.");
$display("If you don't see the message then click the button 'Run All'");
for (i = 0; i < TEST_VALUES; i = i + 1) begin
running_line = line_dump[i*5+:5];
#TIME_OPERATION;
end
$display("FINISH simulation");
$display("FINISH simulation, time == %t", $realtime);
$display(
"Now you should open the waveform window",
"and visually prove correctness of the design"

33
Labs/01. Adder/tb_fulladder32.sv
View File

@@ -39,32 +39,25 @@ parameter TEST_VALUES = 3000;
assign sum_dump = running_line[31:0];
assign carry_o_dump = running_line[32];
`ifdef __debug__
initial begin
$display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop();
for ( i = 0; i < TEST_VALUES; i = i + 1 )
begin
running_line = line_dump[i*98+:98];
#TIME_OPERATION;
if( (tb_carry_o !== carry_o_dump) || (tb_sum_o !== sum_dump) ) begin
$display("ERROR! carry_i = %b; (a)%h + (b)%h = ", tb_carry_i, tb_a_i, tb_b_i, "(carry_o)%b (sum_o)%h;", tb_carry_o, tb_sum_o, " carry_o_dump: %b, sum_dump: %h", carry_o_dump, sum_dump);
err_count = err_count + 1'b1;
end
$timeformat(-9, 2, " ns");
$display("START simulation of 32-bit fulladder.");
$display("You should run simmulation until the message 'FINISH simulation' appears in the log.");
$display("If you don't see the message then click the button 'Run All'");
for ( i = 0; i < TEST_VALUES; i = i + 1 ) begin
running_line = line_dump[i*98+:98];
#TIME_OPERATION;
if( (tb_carry_o !== carry_o_dump) || (tb_sum_o !== sum_dump) ) begin
$display("ERROR! carry_i = %b; (a)%h + (b)%h = ", tb_carry_i, tb_a_i, tb_b_i, "(carry_o)%b (sum_o)%h;", tb_carry_o, tb_sum_o, " carry_o_dump: %b, sum_dump: %h", carry_o_dump, sum_dump, " time == %t", $realtime);
err_count = err_count + 1'b1;
end
end
$display("Number of errors: %d", err_count);
if( !err_count ) $display("\nfulladder32 SUCCESS!!!\n");
$display("FINISH simulation, time == %t", $realtime);
$finish();
end
`else
initial begin
for ( i = 0; i < TEST_VALUES; i = i + 1 )
begin
#TIME_OPERATION;
running_line = line_dump[i*98+:98];
end
$finish();
end
`endif
initial line_dump = {
98'h04854d49302257a06d29e93a6,
98'h2c7c1598c1ae5ec36b8a9d171,

16
Labs/01. Adder/tb_fulladder4.sv
View File

@@ -9,6 +9,8 @@
//////////////////////////////////////////////////////////////////////////////////
module tb_fulladder4();
timeunit 1ns;
timeprecision 1ps;
parameter TIME_OPERATION = 100;
parameter TEST_VALUES = 400;
@@ -40,14 +42,16 @@ module tb_fulladder4();
assign carry_o_dump = running_line[0];
initial begin
$timeformat(-9, 2, " ns");
$display("START simulation of 4-bit fulladder.");
$display("You should run simmulation until the message 'FINISH simulation' appears in the log.");
for ( i = TEST_VALUES-1; i >=0 ; i = i - 1 )
begin
running_line = line_dump[i*14+:14];
#TIME_OPERATION;
end
$display("FINISH simulation");
$display("If you don't see the message then click the button 'Run All'");
for ( i = TEST_VALUES-1; i >=0 ; i = i - 1 ) begin
running_line = line_dump[i*14+:14];
#TIME_OPERATION;
end
$display("FINISH simulation, time == %t", $realtime);
$display(
"Now you should open the waveform window",
"and visually prove correctness of the design"