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ЛР3. Исправление подключения модуля в nexys_rf

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Andrei Solodovnikov
2024-09-09 14:36:28 +03:00
committed by GitHub
parent ffec97f5ac
commit 7b58389d55
1 changed files with 1 additions and 1 deletions
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Labs/03. Register file and memory/board files/nexys_rf_riscv.sv
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@@ -34,7 +34,7 @@ module nexys_rf_riscv(
logic [7:0][3:0] rd1; logic [7:0][3:0] rd1;
logic [7:0][3:0] rd2; logic [7:0][3:0] rd2;
rf_riscv rf_riscv ( register_file rf_riscv (
.clk_i (clk_i), .clk_i (clk_i),
.read_addr1_i (ra1 ), .read_addr1_i (ra1 ),
.read_addr2_i (ra2 ), .read_addr2_i (ra2 ),