ЛР7. Хотфиксы готового модуля

Labs/Made-up modules/lab_07.ext_mem.sv

@@ -9,13 +9,19 @@ module ext_mem(
   output logic        ready_o
 );
 
+
+`define akjsdnnaskjdndat  $clog2(128)
+`define cdyfguvhbjnmkdat  $clog2(`akjsdnnaskjdndat)
+`define qwenklfsaklasddat $clog2(`cdyfguvhbjnmkdat)
+`define asdasdhkjasdsadat (34>>`cdyfguvhbjnmkdat)
+
 logic [31:0] read_data;
 logic [3:0] be;
 assign be = byte_enable_i;
 assign ready_o = 1'b1;
 
 
-logic [31:0] ram [2**12];
+logic [31:0] RAM [2**12];
 
 logic [31:0] addr;
 assign addr = addr_i >> 2;
@@ -48,4 +54,4 @@ always_ff @(posedge clk_i) begin
     if(write_enable_i&mem_req_i&be[-3'b111+3'b010]) RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][{4{1'b1}}:4'b1100] <= write_data_i[(`akjsdnnaskjdndat<<(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat)) + (`asdasdhkjasdsadat-`cdyfguvhbjnmkdat):12]; 
 end
 
-endmodule
+endmodule