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ЛР4. Рефактор демонстрационного модуля
Демонстрационный модуль теперь только один --------- Co-authored-by: Andrei Solodovnikov <VoultBoy@yandex.ru>
This commit is contained in:
BROsandr
GitHub
@@ -2,91 +2,443 @@
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Nikita Bulavin
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* Email(s) : nekkit6@edu.miet.ru
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* Author(s) : Alexander Kharlamov
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* Email(s) : sasha_xarlamov@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module nexys_CYBERcobra_dz(
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input CLK100,
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input resetn,
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input BTND,
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input [15:0] SW,
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output CA, CB, CC, CD, CE, CF, CG,
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output [7:0] AN
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typedef enum {
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INSTR_ALU , // branch and computational
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INSTR_LI , // const load
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INSTR_IN , // periphery load
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INSTR_JUMP ,
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INSTR_NOP // ws == 3
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} Instruction_type;
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typedef enum {
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CH_0 = 0,
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CH_1,
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CH_2,
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CH_3,
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CH_4,
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CH_5,
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CH_6,
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CH_7,
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CH_8,
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CH_9,
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CH_A,
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CH_b,
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CH_c,
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CH_d,
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CH_E,
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CH_F,
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CH_G,
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CH_L,
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CH_n,
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CH_o,
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CH_r,
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CH_S,
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CH_t,
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CH_u,
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CH_X,
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CH_P,
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CH_J,
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CH_q,
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CH_i,
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CH_m,
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CH_SPACE
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} Char;
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typedef struct {
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logic ca;
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logic cb;
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logic cc;
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logic cd;
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logic ce;
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logic cf;
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logic cg;
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logic dp;
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} Semseg;
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module nexys_CYBERcobra(
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input logic clk_i,
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input logic arstn_i,
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input logic [15:0] sw_i,
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input logic btnd_i,
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output logic [15:0] led_o,
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output logic ca_o,
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output logic cb_o,
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output logic cc_o,
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output logic cd_o,
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output logic ce_o,
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output logic cf_o,
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output logic cg_o,
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output logic dp_o,
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output logic [ 7:0] an_o
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);
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logic [31:0] cobra_out;
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logic btnd_sync;
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sync sync (
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.clk_i ,
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.data_i (btnd_i ),
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.data_o (btnd_sync)
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);
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logic btnd_debounce;
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debounce debounce (
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.clk_i ,
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.arstn_i ,
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.data_i (btnd_sync ),
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.data_o (btnd_debounce)
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);
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logic bufg_clk;
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BUFG dut_bufg(
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.I (btnd_debounce),
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.O (bufg_clk )
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);
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CYBERcobra dut (
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.clk_i (bufg_clk ),
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.rst_i (!arstn_i ),
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.sw_i (sw_i ),
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.out_o (cobra_out )
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);
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logic [31:0] instr_addr;
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logic [31:0] instr;
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assign instr_addr = dut.imem.addr_i;
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assign instr = dut.imem.read_data_o;
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import alu_opcodes_pkg::*;
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Instruction_type instr_type;
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logic [ALU_OP_WIDTH-1:0] alu_op;
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logic illegal_instr;
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nexys_CYBERcobra_decoder nexys_CYBERcobra_decoder (
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.instr_i (instr ),
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.instr_type_o (instr_type ),
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.alu_op_o (alu_op ),
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.illegal_instr_o (illegal_instr)
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);
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Char op_chars[0:3];
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always_comb begin
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op_chars = '{4{CH_SPACE}};
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case (instr_type)
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INSTR_ALU:
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case (alu_op)
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ALU_ADD : op_chars[0:2] = '{CH_A, CH_d, CH_d};
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ALU_SUB : op_chars[0:2] = '{CH_S, CH_u, CH_b};
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ALU_XOR : op_chars[0:2] = '{CH_X, CH_o, CH_r};
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ALU_OR : op_chars[0:1] = '{CH_o, CH_r};
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ALU_AND : op_chars[0:2] = '{CH_A, CH_n, CH_d};
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ALU_SRA : op_chars[0:2] = '{CH_S, CH_r, CH_A};
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ALU_SRL : op_chars[0:2] = '{CH_S, CH_r, CH_L};
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ALU_SLL : op_chars[0:2] = '{CH_S, CH_L, CH_L};
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ALU_LTS : op_chars[0:2] = '{CH_L, CH_t, CH_S};
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ALU_LTU : op_chars[0:2] = '{CH_L, CH_t, CH_u};
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ALU_GES : op_chars[0:2] = '{CH_G, CH_E, CH_S};
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ALU_GEU : op_chars[0:2] = '{CH_G, CH_E, CH_u};
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ALU_EQ : op_chars[0:1] = '{CH_E, CH_q};
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ALU_NE : op_chars[0:1] = '{CH_n, CH_E};
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ALU_SLTS: op_chars = '{CH_S, CH_L, CH_t, CH_S};
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ALU_SLTU: op_chars = '{CH_S, CH_L, CH_t, CH_u};
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default : ;
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endcase
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INSTR_LI : op_chars[0:1] = '{CH_L, CH_i};
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INSTR_JUMP: op_chars = '{CH_J, CH_u, CH_m, CH_P};
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INSTR_NOP : op_chars[0:2] = '{CH_n, CH_o, CH_P};
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INSTR_IN : op_chars[0:1] = '{CH_i, CH_n};
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endcase
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end
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Char all_chars[0:7];
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assign all_chars[0:3] = {
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Char'(led_o[7:4]) ,
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Char'(led_o[3:0]) ,
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Char'(instr_addr[7:4]),
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Char'(instr_addr[3:0])
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};
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localparam Char ILL_INSTR_MSG[0:3] = '{CH_i, CH_L, CH_L, CH_SPACE};
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assign all_chars[4:7] = illegal_instr ? ILL_INSTR_MSG : op_chars;
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Semseg all_semsegs[0:7];
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for (genvar semseg_num = 0; semseg_num < 8; ++semseg_num) begin : CHAR2SEMSEG_GEN
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char2semseg char2semseg (
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.char_i (all_chars [semseg_num]),
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.semseg_o (all_semsegs[semseg_num])
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);
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CYBERcobra dut(
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.clk_i(btn),
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.rst_i(!resetn),
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.sw_i(SW[15:0]),
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.out_o(out)
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);
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localparam pwm = 1000;
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reg [9:0] counter;
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reg [3:0] semseg;
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reg [7:0] ANreg;
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reg CAr, CBr, CCr, CDr, CEr, CFr, CGr;
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reg btn;
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wire [31:0] out;
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assign AN[7:0] = ANreg[7:0];
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assign {CA, CB, CC, CD, CE, CF, CG} = {CAr, CBr, CCr, CDr, CEr, CFr, CGr};
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end
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always @(posedge CLK100) begin
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if (!resetn) begin
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counter <= 'b0;
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ANreg[7:0] <= 8'b11111111;
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{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111;
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btn <= BTND;
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Semseg all_semsegs_dotted[0:7];
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assign all_semsegs_dotted[0] = all_semsegs[0];
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assign all_semsegs_dotted[2:7] = all_semsegs[2:7];
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assign all_semsegs_dotted[1].ca = all_semsegs[1].ca;
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assign all_semsegs_dotted[1].cb = all_semsegs[1].cb;
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assign all_semsegs_dotted[1].cc = all_semsegs[1].cc;
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assign all_semsegs_dotted[1].cd = all_semsegs[1].cd;
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assign all_semsegs_dotted[1].ce = all_semsegs[1].ce;
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assign all_semsegs_dotted[1].cf = all_semsegs[1].cf;
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assign all_semsegs_dotted[1].cg = all_semsegs[1].cg;
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assign all_semsegs_dotted[1].dp = 1'b0;
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Semseg current_semseg;
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logic [7:0] an;
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semseg_one2many semseg_one2many (
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.clk100m_i (clk_i ),
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.arstn_i (arstn_i ),
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.all_semsegs_i (all_semsegs_dotted),
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.current_semseg_o (current_semseg ),
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.an_o (an )
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);
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assign ca_o = current_semseg.ca;
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assign cb_o = current_semseg.cb;
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assign cc_o = current_semseg.cc;
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assign cd_o = current_semseg.cd;
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assign ce_o = current_semseg.ce;
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assign cf_o = current_semseg.cf;
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assign cg_o = current_semseg.cg;
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assign dp_o = current_semseg.dp;
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assign an_o = an;
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assign led_o = cobra_out[15:0];
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endmodule
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module nexys_CYBERcobra_decoder
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import alu_opcodes_pkg::*;
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(
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input logic [31:0] instr_i,
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output Instruction_type instr_type_o,
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output logic [ALU_OP_WIDTH-1:0] alu_op_o,
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output logic illegal_instr_o
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);
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logic j;
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logic b;
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logic [1:0] ws;
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assign j = instr_i[31];
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assign b = instr_i[30];
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assign ws = instr_i[29:28];
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logic is_branch_instr;
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assign is_branch_instr = b;
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always_comb begin
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instr_type_o = INSTR_NOP;
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if (j) begin
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instr_type_o = INSTR_JUMP;
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end else if (b) begin
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instr_type_o = INSTR_ALU;
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end else begin
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case (ws)
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2'd0: instr_type_o = INSTR_LI;
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2'd1: instr_type_o = INSTR_ALU;
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2'd2: instr_type_o = INSTR_IN;
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2'd3: instr_type_o = INSTR_NOP;
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endcase
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end
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else begin
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btn <= BTND;
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if (counter < pwm) counter = counter + 'b1;
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else begin
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counter = 'b0;
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ANreg[1] <= ANreg[0];
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ANreg[2] <= ANreg[1];
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ANreg[3] <= ANreg[2];
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ANreg[4] <= ANreg[3];
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ANreg[5] <= ANreg[4];
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ANreg[6] <= ANreg[5];
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ANreg[7] <= ANreg[6];
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ANreg[0] <= !(ANreg[6:0] == 7'b1111111);
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end
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case (1'b0)
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ANreg[0]: semseg <= out[3 : 0];
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ANreg[1]: semseg <= out[7 : 4];
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ANreg[2]: semseg <= out[11: 8];
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ANreg[3]: semseg <= out[15:12];
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ANreg[4]: semseg <= out[19:16];
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ANreg[5]: semseg <= out[23:20];
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ANreg[6]: semseg <= out[27:24];
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ANreg[7]: semseg <= out[31:28];
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endcase
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case (semseg)
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4'h0: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001;
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4'h1: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001111;
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4'h2: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0010010;
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4'h3: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000110;
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4'h4: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001100;
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4'h5: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100100;
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4'h6: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100000;
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4'h7: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001111;
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4'h8: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000000;
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4'h9: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000100;
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4'hA: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000;
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4'hB: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1100000;
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4'hC: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110001;
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4'hD: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000010;
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4'hE: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110000;
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4'hF: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0111000;
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default: {CAr,CBr,CCr,CDr, CEr, CFr, CGr} <= 7'b0111111;
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endcase
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end
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end
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assign alu_op_o = instr_i[27:23];
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import alu_opcodes_pkg::*;
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typedef enum {
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ALU_OP_BRANCH,
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ALU_OP_COMPUTATIONAL,
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ALU_OP_ILLEGAL
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} Alu_op_type;
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Alu_op_type alu_op_type;
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always_comb begin
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alu_op_type = ALU_OP_ILLEGAL;
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case (alu_op_o) inside
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ALU_LTS,
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ALU_LTU,
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ALU_GES,
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ALU_GEU,
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ALU_EQ ,
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ALU_NE : alu_op_type = ALU_OP_BRANCH;
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ALU_ADD ,
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ALU_SUB ,
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ALU_XOR ,
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ALU_OR ,
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ALU_AND ,
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ALU_SRA ,
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ALU_SRL ,
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ALU_SLL ,
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ALU_SLTS,
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ALU_SLTU: alu_op_type = ALU_OP_COMPUTATIONAL;
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default : alu_op_type = ALU_OP_ILLEGAL;
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endcase
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end
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assign illegal_instr_o = (instr_type_o == INSTR_ALU) && ((alu_op_type == ALU_OP_ILLEGAL) ||
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((alu_op_type == ALU_OP_BRANCH) ^ is_branch_instr));
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endmodule
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module char2semseg #(
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parameter bit HEX_ONLY = 1'b0
|
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) (
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input Char char_i,
|
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output Semseg semseg_o
|
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);
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|
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localparam bit [6:0] BLANK = '1;
|
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|
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logic [6:0] semseg;
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always_comb begin
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case (char_i)
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CH_0 : semseg = ~7'h3F;
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CH_1 : semseg = ~7'h06;
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CH_2 : semseg = ~7'h5B;
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CH_3 : semseg = ~7'h4F;
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CH_4 : semseg = ~7'h66;
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CH_5 : semseg = ~7'h6D;
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CH_6 : semseg = ~7'h7D;
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CH_7 : semseg = ~7'h07;
|
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CH_8 : semseg = ~7'h7F;
|
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CH_9 : semseg = ~7'h6F;
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CH_A : semseg = ~7'h5F;
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CH_b : semseg = ~7'h7C;
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CH_c : semseg = ~7'h58;
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CH_d : semseg = ~7'h5E;
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CH_E : semseg = ~7'h79;
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CH_F : semseg = ~7'h71;
|
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CH_G : semseg = ~7'h3D;
|
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CH_L : semseg = ~7'h38;
|
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CH_n : semseg = ~7'h54;
|
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CH_o : semseg = ~7'h5C;
|
||||
CH_r : semseg = ~7'h50;
|
||||
CH_S : semseg = ~7'h64;
|
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CH_t : semseg = ~7'h78;
|
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CH_u : semseg = ~7'h1C;
|
||||
CH_X : semseg = ~7'h76;
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CH_P : semseg = ~7'h73;
|
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CH_J : semseg = ~7'h1E;
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CH_q : semseg = ~7'h67;
|
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CH_i : semseg = ~7'h30;
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CH_m : semseg = ~7'h77;
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default : semseg = BLANK;
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endcase
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||||
end
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||||
|
||||
assign semseg_o.ca = semseg[0];
|
||||
assign semseg_o.cb = semseg[1];
|
||||
assign semseg_o.cc = semseg[2];
|
||||
assign semseg_o.cd = semseg[3];
|
||||
assign semseg_o.ce = semseg[4];
|
||||
assign semseg_o.cf = semseg[5];
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||||
assign semseg_o.cg = semseg[6];
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assign semseg_o.dp = 1'b1;
|
||||
|
||||
endmodule
|
||||
|
||||
module semseg_one2many #(
|
||||
parameter int unsigned SEMSEGS_NUM = 8
|
||||
) (
|
||||
input Semseg all_semsegs_i[0:SEMSEGS_NUM-1],
|
||||
input logic clk100m_i,
|
||||
input logic arstn_i,
|
||||
output Semseg current_semseg_o,
|
||||
output logic [7:0] an_o
|
||||
);
|
||||
logic clk_i;
|
||||
assign clk_i = clk100m_i;
|
||||
|
||||
localparam int COUNTER_WIDTH = 10;
|
||||
logic [COUNTER_WIDTH-1:0] counter_next;
|
||||
logic [COUNTER_WIDTH-1:0] counter_ff;
|
||||
assign counter_next = counter_ff + COUNTER_WIDTH'('b1);
|
||||
always_ff @(posedge clk_i or negedge arstn_i) begin
|
||||
if (!arstn_i) counter_ff <= '0;
|
||||
else counter_ff <= counter_next;
|
||||
end
|
||||
|
||||
logic [7:0] an_ff;
|
||||
logic [7:0] an_next;
|
||||
logic an_en;
|
||||
assign an_next = {an_ff[$left(an_ff)-1:0], an_ff[$left(an_ff)]};
|
||||
assign an_en = ~|counter_ff;
|
||||
always_ff @(posedge clk_i or negedge arstn_i) begin
|
||||
if (!arstn_i) an_ff <= ~8'b1;
|
||||
else if (an_en) an_ff <= an_next;
|
||||
end
|
||||
|
||||
Semseg current_semseg;
|
||||
always_comb begin
|
||||
unique case (1'b0)
|
||||
an_ff[0]: current_semseg = all_semsegs_i[7];
|
||||
an_ff[1]: current_semseg = all_semsegs_i[6];
|
||||
an_ff[2]: current_semseg = all_semsegs_i[5];
|
||||
an_ff[3]: current_semseg = all_semsegs_i[4];
|
||||
an_ff[4]: current_semseg = all_semsegs_i[3];
|
||||
an_ff[5]: current_semseg = all_semsegs_i[2];
|
||||
an_ff[6]: current_semseg = all_semsegs_i[1];
|
||||
an_ff[7]: current_semseg = all_semsegs_i[0];
|
||||
endcase
|
||||
end
|
||||
|
||||
assign current_semseg_o = current_semseg;
|
||||
|
||||
assign an_o = an_ff;
|
||||
|
||||
endmodule
|
||||
|
||||
module debounce #(
|
||||
parameter int unsigned MAX_COUNT = 10000
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic arstn_i,
|
||||
input logic data_i,
|
||||
output logic data_o
|
||||
);
|
||||
|
||||
localparam int COUNTER_WIDTH = $clog2(MAX_COUNT);
|
||||
logic [COUNTER_WIDTH-1:0] counter_next;
|
||||
logic [COUNTER_WIDTH-1:0] counter_ff;
|
||||
assign counter_next = (data_o != data_i) ? counter_ff - COUNTER_WIDTH'('b1) :
|
||||
COUNTER_WIDTH'(MAX_COUNT);
|
||||
always_ff @(posedge clk_i or negedge arstn_i) begin
|
||||
if (!arstn_i) counter_ff <= COUNTER_WIDTH'(MAX_COUNT);
|
||||
else counter_ff <= counter_next;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk_i or negedge arstn_i) begin
|
||||
if (!arstn_i) data_o <= '0;
|
||||
else if (~|counter_ff) data_o <= data_i;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module sync #(
|
||||
parameter int unsigned SYNC_STAGES = 3
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic data_i,
|
||||
output logic data_o
|
||||
);
|
||||
|
||||
logic [SYNC_STAGES-1:0] sync_buffer_ff;
|
||||
logic [SYNC_STAGES-1:0] sync_buffer_next;
|
||||
assign sync_buffer_next = {sync_buffer_ff[$left(sync_buffer_ff)-1:0], data_i};
|
||||
always_ff @(posedge clk_i) begin
|
||||
sync_buffer_ff <= sync_buffer_next;
|
||||
end
|
||||
|
||||
assign data_o = sync_buffer_ff[$left(sync_buffer_ff)];
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user