diff --git a/.pic/Labs/board files/nexys_cobra.jpg b/.pic/Labs/board files/nexys_cobra.jpg deleted file mode 100644 index e1e934f..0000000 Binary files a/.pic/Labs/board files/nexys_cobra.jpg and /dev/null differ diff --git a/.pic/Labs/board files/nexys_cobra_operations.drawio.svg b/.pic/Labs/board files/nexys_cobra_operations.drawio.svg new file mode 100644 index 0000000..299711c --- /dev/null +++ b/.pic/Labs/board files/nexys_cobra_operations.drawio.svg @@ -0,0 +1,4 @@ + + + +
- ADD
- SUB
- XOR
- OR
- AND
- SRA
- SRL
- SLL
- LTS
- LTU
- GES
- GEU
- EQ
- NE
- SLTS
- SLTU
- IN
- JUMP
- LI
- ILL
- NOP
 \ No newline at end of file diff --git a/.pic/Labs/board files/nexys_cobra_structure.drawio.svg b/.pic/Labs/board files/nexys_cobra_structure.drawio.svg new file mode 100644 index 0000000..6aae985 --- /dev/null +++ b/.pic/Labs/board files/nexys_cobra_structure.drawio.svg @@ -0,0 +1,4 @@ + + + +
operation
nexys_CYBERcobra
semseg
sw_i
rst_i
decoder
out
PC
operation
instr_mem
read_data_o
add_i
CYBERcobra
out_o

clk_i

16
/
32
/
8
/
[7:0]
16
/
8
/
32
/
[7:0]
[15:0]
out
PC
 \ No newline at end of file diff --git a/Labs/04. Primitive programmable device/board files/README.md b/Labs/04. Primitive programmable device/board files/README.md index 98ffaf8..7618f4f 100644 --- a/Labs/04. Primitive programmable device/board files/README.md +++ b/Labs/04. Primitive programmable device/board files/README.md @@ -1,11 +1,67 @@ # Проверка работы CYBERcobra на ПЛИС -Если вы не понимаете, что лежит в этой папке, или если надо вспомнить, как прошить ПЛИС, можно воспользоваться [`этой инструкцией`](../../../Vivado%20Basics/Program%20nexys%20a7.md) +После того, как вы проверили на моделировании дизайн, вам необходимо проверить его работу на прототипе в ПЛИС. -Файл [`nexys_cybercobra_demo.sv`](nexys_cybercobra_demo.sv), который нужно запускать с [`демонстрационным файлом инструкций`](demo.mem), является демонстрацией возможностей кобры, реализующий лишь декодирование выходных значений в формат для отображения на семисегментных индикаторах, а вся логика работы реализована инструкциями в текстовом файле. +Инструкция по реализации прототипа описана [здесь](../../../Vivado%20Basics/How%20to%20program%20an%20fpga%20board.md). -Сначала выводится приветствие `≡ALOHA≡`, меняя положение восьми правых переключателей, последовательно нажимая на кнопку `BTND` (на рисунке выделена синим цветом), можно включать или выключать `один` из выбранных сегментов. Кнопка `CPU RESET` (на рисунке выделена красным цветом) возвращает все исходное состояние. Попробуйте погасить все слово, а потом снова его зажечь. +На _рис. 1_ представлена схема прототипа в ПЛИС. -Файл [`nexys_cybercobra.sv`](nexys_cybercobra.sv), который нужно запускать с `вашим файлом инструкций`, так же реализует лишь декодирование выходных значений в формат для отображения на семисегментных индикаторах, но кнопка `BTND` задает тактирующий сигнал, следовательно, нажимая на нее, вы можете пошагово переходить по инструкциям, контролируя правильность работы устройства, для удобства можете в тестовом окружении выставить такое же входное значение, как переключатели sw[15:0] на плате. +![../../../.pic/Labs/board%20files/nexys_cobra_structure.drawio.svg](../../../.pic/Labs/board%20files/nexys_cobra_structure.drawio.svg) -![кобра](../../../.pic/Labs/board%20files/nexys_cobra.jpg) +_Рисунок 1. Структурная схема модуля `nexys_CYBERcobra`._ + +Прототип позволяет потактово исполнять программу, прошитую в память инструкций. Также прототип отображает операцию исполняемую в данный момент. + +> [!NOTE] +> Объект модуля `instr_mem` в модуле `CYBERcobra` **должен** называться `imem`. Т.е. строка создания сущности модуля должна выглядеть следующим образом: `instr_mem  imem(...)`. + +## Описание используемой периферии + +- ### Переключатели. + + Значение с переключателей `SW[15:0]` подаются напрямую на порт `sw_i` модуля дизайна. + +- ### Кнопки + + - `BTND` — при нажатии создает тактовый импульс, поступающий на порт тактирования `clk_i` модуля дизайна. + - `CPU_RESET` — соединен со входом `rst_i` модуля дизайна. + +- ### Светодиоды + + Светодиоды `LED[15:0]` отображают младшие 16 бит значения, выставленного в данный момент на порте `out_o` модуля дизайна. + +- ### Семисегментные индикаторы + + Семисегментные индикаторы разбиты на 3 блока (см. _рис. 1_): + + - `out` — отображают младшие 8 бит значения, выставленного в данный момент на порте `out_o` модуля дизайна, в виде шестнадцатеричного числа. + - `PC` — отображают в виде шестнадцатеричного числа младшие 8 бит программного счетчика, который подается на вход `addr_i` модуля памяти инструкций. + - `operation` — отображают [операцию](#операции-отображаемые-прототипом), исполняемую процессором на текущем такте. + +## Операции, отображаемые прототипом + +Соответствие типа инструкции отображаемой операции: + +1. Вычислительные — соответствует опкодам вычислительных операций АЛУ. +1. Инструкция загрузки константы — `LI` (от **l**oad **i**mmediate). +1. Инструкция загрузки из внешних устройств — `IN` (от **in**put). +1. Безусловный переход — `JUMP`. +1. Инструкций условного перехода — соответствует опкодам операций сравнения АЛУ. + +Во время исполнения вычислительных инструкций и инструкций условного перехода могут встретиться нелегальные операции (отображается как `ILL`, от **ill**egal). Операция считается нелегальной в следующих случаях: + +- Если в поле инструкции, отвечающем за операция АЛУ, указана битовая последовательность, не входящая в диапазон допустимых значений. +- Если инструкция является вычислительной, но в поле инструкции, отвечающем за операция АЛУ, указана битовая последовательность, соответствующая операции, вычисляющей флаг. И обратный случай. + +Инструкция `0 0 11 xxxxxxxxxxxxxxxxxxxxxxxxxxxx` отображается как `NOP` (от **n**o **op**eration). + +Соответствие операции ее отображению на семисегментных индикаторах представлено на _рис. 2_: + +!['../../../.pic/Labs/board%20files/nexys_cobra_operations.drawio.svg'](../../../.pic/Labs/board%20files/nexys_cobra_operations.drawio.svg) + +_Рисунок 2. Соответствие операции ее отображению на семисегментных индикаторах._ + + +## Демонстрационная программа + +В качестве демонстрационной программы, предлагается использовать [example.mem](../example.mem). Описание ее работы можно прочитать в разделе [#финальный обзор](../README.md#финальный-обзор). diff --git a/Labs/04. Primitive programmable device/board files/demo.mem b/Labs/04. Primitive programmable device/board files/demo.mem deleted file mode 100644 index c721581..0000000 --- a/Labs/04. Primitive programmable device/board files/demo.mem +++ /dev/null @@ -1,95 +0,0 @@ -00074221 -00000202 -10844001 -00119463 -10046001 -0006000c -0001400d -0000020e -0000002f -10b0400c -10b4400d -10b8400e -10bc400f -00100010 -00018011 -00001412 -00000073 -00000022 -00000043 -00000084 -00000105 -00000206 -00000407 -00000808 -00001009 -00001fea -2004000b -30040000 -30040000 -30040000 -30040000 -30040000 -30040000 -30040000 -30040000 -30040000 -7ea97ec0 -13ad400b -7c2c4520 -7c2c6540 -7c2c8560 -7c2ca580 -7c2cc5a0 -7c2ce5c0 -7c2d05e0 -7c2d2600 -13866014 -7c500200 -13864014 -7c500200 -13862014 -7c500200 -13860014 -7c500200 -1385e014 -7c500200 -1385c014 -7c500200 -1385a014 -7c500200 -13858014 -7c500200 -bc040400 -13066001 -bc0403c0 -13064001 -bc040380 -13062001 -bc040340 -13060001 -bc040300 -1305e001 -bc0402c0 -1305c001 -bc040280 -1305a001 -bc040240 -13058001 -bc040200 -12066001 -bc0401c0 -12064001 -bc040180 -12062001 -bc040140 -12060001 -bc040100 -1205e001 -bc0400c0 -1205c001 -bc040080 -1205a001 -bc040040 -12058001 -bc041760 diff --git a/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc b/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc index 7c1538a..1b7a70b 100644 --- a/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc +++ b/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc @@ -4,47 +4,47 @@ ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project # Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100 }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100}]; +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_i}]; #Switches -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] -set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw_i[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw_i[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw_i[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw_i[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw_i[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw_i[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw_i[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw_i[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw_i[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw_i[9] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw_i[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw_i[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw_i[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw_i[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw_i[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw_i[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] ### LEDs -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led_o[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led_o[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led_o[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led_o[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led_o[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led_o[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led_o[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led_o[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led_o[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led_o[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led_o[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led_o[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led_o[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led_o[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led_o[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led_o[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] -### RGB LEDs +## RGB LEDs #set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b #set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g #set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r @@ -53,30 +53,30 @@ set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r ##7 segment display -set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca -set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb -set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc -set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd -set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce -set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf -set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp -set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] -set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca_o }]; #IO_L24N_T3_A00_D16_14 Sch=ca +set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb_o }]; #IO_25_14 Sch=cb +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc_o }]; #IO_25_15 Sch=cc +set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd_o }]; #IO_L17P_T2_A26_15 Sch=cd +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce_o }]; #IO_L13P_T2_MRCC_14 Sch=ce +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf_o }]; #IO_L19P_T3_A10_D26_14 Sch=cf +set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg_o }]; #IO_L4P_T0_D04_14 Sch=cg +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp_o }]; #IO_L19N_T3_A21_VREF_15 Sch=dp +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an_o[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an_o[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an_o[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an_o[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an_o[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an_o[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an_o[6] }]; #IO_L23P_T3_35 Sch=an[6] +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an_o[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] ##Buttons -set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn +set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { arstn_i }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn #set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc #set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu #set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd +# set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr_i }]; #IO_L10N_T1_D15_14 Sch=btnr +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd_i }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd ##Pmod Headers @@ -208,4 +208,4 @@ set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND } #set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn \ No newline at end of file +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn diff --git a/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv b/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv index acd1107..7d14ae3 100644 --- a/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv +++ b/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv @@ -2,91 +2,443 @@ * Project Name : Architectures of Processor Systems (APS) lab work * Organization : National Research University of Electronic Technology (MIET) * Department : Institute of Microdevices and Control Systems -* Author(s) : Nikita Bulavin -* Email(s) : nekkit6@edu.miet.ru +* Author(s) : Alexander Kharlamov +* Email(s) : sasha_xarlamov@org.miet.ru See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. * ------------------------------------------------------------------------------ */ -module nexys_CYBERcobra_dz( - input CLK100, - input resetn, - input BTND, - input [15:0] SW, - output CA, CB, CC, CD, CE, CF, CG, - output [7:0] AN +typedef enum { + INSTR_ALU , // branch and computational + INSTR_LI , // const load + INSTR_IN , // periphery load + INSTR_JUMP , + INSTR_NOP // ws == 3 +} Instruction_type; + +typedef enum { + CH_0 = 0, + CH_1, + CH_2, + CH_3, + CH_4, + CH_5, + CH_6, + CH_7, + CH_8, + CH_9, + CH_A, + CH_b, + CH_c, + CH_d, + CH_E, + CH_F, + CH_G, + CH_L, + CH_n, + CH_o, + CH_r, + CH_S, + CH_t, + CH_u, + CH_X, + CH_P, + CH_J, + CH_q, + CH_i, + CH_m, + + CH_SPACE +} Char; + +typedef struct { + logic ca; + logic cb; + logic cc; + logic cd; + logic ce; + logic cf; + logic cg; + logic dp; +} Semseg; + +module nexys_CYBERcobra( + input logic clk_i, + input logic arstn_i, + input logic [15:0] sw_i, + input logic btnd_i, + output logic [15:0] led_o, + output logic ca_o, + output logic cb_o, + output logic cc_o, + output logic cd_o, + output logic ce_o, + output logic cf_o, + output logic cg_o, + output logic dp_o, + output logic [ 7:0] an_o +); + + logic [31:0] cobra_out; + + logic btnd_sync; + sync sync ( + .clk_i , + .data_i (btnd_i ), + .data_o (btnd_sync) + ); + logic btnd_debounce; + debounce debounce ( + .clk_i , + .arstn_i , + .data_i (btnd_sync ), + .data_o (btnd_debounce) + ); + logic bufg_clk; + BUFG dut_bufg( + .I (btnd_debounce), + .O (bufg_clk ) + ); + + CYBERcobra dut ( + .clk_i (bufg_clk ), + .rst_i (!arstn_i ), + .sw_i (sw_i ), + .out_o (cobra_out ) + ); + + logic [31:0] instr_addr; + logic [31:0] instr; + assign instr_addr = dut.imem.addr_i; + assign instr = dut.imem.read_data_o; + + import alu_opcodes_pkg::*; + + Instruction_type instr_type; + logic [ALU_OP_WIDTH-1:0] alu_op; + logic illegal_instr; + nexys_CYBERcobra_decoder nexys_CYBERcobra_decoder ( + .instr_i (instr ), + .instr_type_o (instr_type ), + .alu_op_o (alu_op ), + .illegal_instr_o (illegal_instr) + ); + + Char op_chars[0:3]; + always_comb begin + op_chars = '{4{CH_SPACE}}; + + case (instr_type) + INSTR_ALU: + case (alu_op) + ALU_ADD : op_chars[0:2] = '{CH_A, CH_d, CH_d}; + ALU_SUB : op_chars[0:2] = '{CH_S, CH_u, CH_b}; + ALU_XOR : op_chars[0:2] = '{CH_X, CH_o, CH_r}; + ALU_OR : op_chars[0:1] = '{CH_o, CH_r}; + ALU_AND : op_chars[0:2] = '{CH_A, CH_n, CH_d}; + ALU_SRA : op_chars[0:2] = '{CH_S, CH_r, CH_A}; + ALU_SRL : op_chars[0:2] = '{CH_S, CH_r, CH_L}; + ALU_SLL : op_chars[0:2] = '{CH_S, CH_L, CH_L}; + ALU_LTS : op_chars[0:2] = '{CH_L, CH_t, CH_S}; + ALU_LTU : op_chars[0:2] = '{CH_L, CH_t, CH_u}; + ALU_GES : op_chars[0:2] = '{CH_G, CH_E, CH_S}; + ALU_GEU : op_chars[0:2] = '{CH_G, CH_E, CH_u}; + ALU_EQ : op_chars[0:1] = '{CH_E, CH_q}; + ALU_NE : op_chars[0:1] = '{CH_n, CH_E}; + ALU_SLTS: op_chars = '{CH_S, CH_L, CH_t, CH_S}; + ALU_SLTU: op_chars = '{CH_S, CH_L, CH_t, CH_u}; + + default : ; + endcase + INSTR_LI : op_chars[0:1] = '{CH_L, CH_i}; + INSTR_JUMP: op_chars = '{CH_J, CH_u, CH_m, CH_P}; + INSTR_NOP : op_chars[0:2] = '{CH_n, CH_o, CH_P}; + INSTR_IN : op_chars[0:1] = '{CH_i, CH_n}; + endcase + end + + Char all_chars[0:7]; + assign all_chars[0:3] = { + Char'(led_o[7:4]) , + Char'(led_o[3:0]) , + Char'(instr_addr[7:4]), + Char'(instr_addr[3:0]) + }; + localparam Char ILL_INSTR_MSG[0:3] = '{CH_i, CH_L, CH_L, CH_SPACE}; + assign all_chars[4:7] = illegal_instr ? ILL_INSTR_MSG : op_chars; + + Semseg all_semsegs[0:7]; + for (genvar semseg_num = 0; semseg_num < 8; ++semseg_num) begin : CHAR2SEMSEG_GEN + char2semseg char2semseg ( + .char_i (all_chars [semseg_num]), + .semseg_o (all_semsegs[semseg_num]) ); - - CYBERcobra dut( - .clk_i(btn), - .rst_i(!resetn), - .sw_i(SW[15:0]), - .out_o(out) - ); - -localparam pwm = 1000; -reg [9:0] counter; -reg [3:0] semseg; -reg [7:0] ANreg; -reg CAr, CBr, CCr, CDr, CEr, CFr, CGr; -reg btn; -wire [31:0] out; - -assign AN[7:0] = ANreg[7:0]; -assign {CA, CB, CC, CD, CE, CF, CG} = {CAr, CBr, CCr, CDr, CEr, CFr, CGr}; + end -always @(posedge CLK100) begin - if (!resetn) begin - counter <= 'b0; - ANreg[7:0] <= 8'b11111111; - {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; - btn <= BTND; + Semseg all_semsegs_dotted[0:7]; + assign all_semsegs_dotted[0] = all_semsegs[0]; + assign all_semsegs_dotted[2:7] = all_semsegs[2:7]; + assign all_semsegs_dotted[1].ca = all_semsegs[1].ca; + assign all_semsegs_dotted[1].cb = all_semsegs[1].cb; + assign all_semsegs_dotted[1].cc = all_semsegs[1].cc; + assign all_semsegs_dotted[1].cd = all_semsegs[1].cd; + assign all_semsegs_dotted[1].ce = all_semsegs[1].ce; + assign all_semsegs_dotted[1].cf = all_semsegs[1].cf; + assign all_semsegs_dotted[1].cg = all_semsegs[1].cg; + assign all_semsegs_dotted[1].dp = 1'b0; + + Semseg current_semseg; + logic [7:0] an; + semseg_one2many semseg_one2many ( + .clk100m_i (clk_i ), + .arstn_i (arstn_i ), + .all_semsegs_i (all_semsegs_dotted), + .current_semseg_o (current_semseg ), + .an_o (an ) + ); + + assign ca_o = current_semseg.ca; + assign cb_o = current_semseg.cb; + assign cc_o = current_semseg.cc; + assign cd_o = current_semseg.cd; + assign ce_o = current_semseg.ce; + assign cf_o = current_semseg.cf; + assign cg_o = current_semseg.cg; + assign dp_o = current_semseg.dp; + + assign an_o = an; + + assign led_o = cobra_out[15:0]; + +endmodule + +module nexys_CYBERcobra_decoder + import alu_opcodes_pkg::*; +( + input logic [31:0] instr_i, + output Instruction_type instr_type_o, + output logic [ALU_OP_WIDTH-1:0] alu_op_o, + output logic illegal_instr_o +); + + logic j; + logic b; + logic [1:0] ws; + + assign j = instr_i[31]; + assign b = instr_i[30]; + assign ws = instr_i[29:28]; + + logic is_branch_instr; + assign is_branch_instr = b; + + always_comb begin + instr_type_o = INSTR_NOP; + + if (j) begin + instr_type_o = INSTR_JUMP; + end else if (b) begin + instr_type_o = INSTR_ALU; + end else begin + case (ws) + 2'd0: instr_type_o = INSTR_LI; + 2'd1: instr_type_o = INSTR_ALU; + 2'd2: instr_type_o = INSTR_IN; + 2'd3: instr_type_o = INSTR_NOP; + endcase end - else begin - btn <= BTND; - if (counter < pwm) counter = counter + 'b1; - else begin - counter = 'b0; - ANreg[1] <= ANreg[0]; - ANreg[2] <= ANreg[1]; - ANreg[3] <= ANreg[2]; - ANreg[4] <= ANreg[3]; - ANreg[5] <= ANreg[4]; - ANreg[6] <= ANreg[5]; - ANreg[7] <= ANreg[6]; - ANreg[0] <= !(ANreg[6:0] == 7'b1111111); - end - case (1'b0) - ANreg[0]: semseg <= out[3 : 0]; - ANreg[1]: semseg <= out[7 : 4]; - ANreg[2]: semseg <= out[11: 8]; - ANreg[3]: semseg <= out[15:12]; - ANreg[4]: semseg <= out[19:16]; - ANreg[5]: semseg <= out[23:20]; - ANreg[6]: semseg <= out[27:24]; - ANreg[7]: semseg <= out[31:28]; - endcase - case (semseg) - 4'h0: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; - 4'h1: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001111; - 4'h2: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0010010; - 4'h3: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000110; - 4'h4: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001100; - 4'h5: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100100; - 4'h6: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100000; - 4'h7: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001111; - 4'h8: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000000; - 4'h9: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000100; - 4'hA: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; - 4'hB: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1100000; - 4'hC: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110001; - 4'hD: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000010; - 4'hE: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110000; - 4'hF: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0111000; - default: {CAr,CBr,CCr,CDr, CEr, CFr, CGr} <= 7'b0111111; - endcase - end + end + + assign alu_op_o = instr_i[27:23]; + + import alu_opcodes_pkg::*; + + typedef enum { + ALU_OP_BRANCH, + ALU_OP_COMPUTATIONAL, + ALU_OP_ILLEGAL + } Alu_op_type; + Alu_op_type alu_op_type; + always_comb begin + alu_op_type = ALU_OP_ILLEGAL; + + case (alu_op_o) inside + ALU_LTS, + ALU_LTU, + ALU_GES, + ALU_GEU, + ALU_EQ , + ALU_NE : alu_op_type = ALU_OP_BRANCH; + + ALU_ADD , + ALU_SUB , + ALU_XOR , + ALU_OR , + ALU_AND , + ALU_SRA , + ALU_SRL , + ALU_SLL , + ALU_SLTS, + ALU_SLTU: alu_op_type = ALU_OP_COMPUTATIONAL; + + default : alu_op_type = ALU_OP_ILLEGAL; + endcase + end + + assign illegal_instr_o = (instr_type_o == INSTR_ALU) && ((alu_op_type == ALU_OP_ILLEGAL) || + ((alu_op_type == ALU_OP_BRANCH) ^ is_branch_instr)); +endmodule + +module char2semseg #( + parameter bit HEX_ONLY = 1'b0 +) ( + input Char char_i, + output Semseg semseg_o +); + + localparam bit [6:0] BLANK = '1; + + logic [6:0] semseg; + always_comb begin + case (char_i) + CH_0 : semseg = ~7'h3F; + CH_1 : semseg = ~7'h06; + CH_2 : semseg = ~7'h5B; + CH_3 : semseg = ~7'h4F; + CH_4 : semseg = ~7'h66; + CH_5 : semseg = ~7'h6D; + CH_6 : semseg = ~7'h7D; + CH_7 : semseg = ~7'h07; + CH_8 : semseg = ~7'h7F; + CH_9 : semseg = ~7'h6F; + CH_A : semseg = ~7'h5F; + CH_b : semseg = ~7'h7C; + CH_c : semseg = ~7'h58; + CH_d : semseg = ~7'h5E; + CH_E : semseg = ~7'h79; + CH_F : semseg = ~7'h71; + CH_G : semseg = ~7'h3D; + CH_L : semseg = ~7'h38; + CH_n : semseg = ~7'h54; + CH_o : semseg = ~7'h5C; + CH_r : semseg = ~7'h50; + CH_S : semseg = ~7'h64; + CH_t : semseg = ~7'h78; + CH_u : semseg = ~7'h1C; + CH_X : semseg = ~7'h76; + CH_P : semseg = ~7'h73; + CH_J : semseg = ~7'h1E; + CH_q : semseg = ~7'h67; + CH_i : semseg = ~7'h30; + CH_m : semseg = ~7'h77; + default : semseg = BLANK; + endcase + end + + assign semseg_o.ca = semseg[0]; + assign semseg_o.cb = semseg[1]; + assign semseg_o.cc = semseg[2]; + assign semseg_o.cd = semseg[3]; + assign semseg_o.ce = semseg[4]; + assign semseg_o.cf = semseg[5]; + assign semseg_o.cg = semseg[6]; + assign semseg_o.dp = 1'b1; + +endmodule + +module semseg_one2many #( + parameter int unsigned SEMSEGS_NUM = 8 +) ( + input Semseg all_semsegs_i[0:SEMSEGS_NUM-1], + input logic clk100m_i, + input logic arstn_i, + output Semseg current_semseg_o, + output logic [7:0] an_o +); + logic clk_i; + assign clk_i = clk100m_i; + + localparam int COUNTER_WIDTH = 10; + logic [COUNTER_WIDTH-1:0] counter_next; + logic [COUNTER_WIDTH-1:0] counter_ff; + assign counter_next = counter_ff + COUNTER_WIDTH'('b1); + always_ff @(posedge clk_i or negedge arstn_i) begin + if (!arstn_i) counter_ff <= '0; + else counter_ff <= counter_next; + end + + logic [7:0] an_ff; + logic [7:0] an_next; + logic an_en; + assign an_next = {an_ff[$left(an_ff)-1:0], an_ff[$left(an_ff)]}; + assign an_en = ~|counter_ff; + always_ff @(posedge clk_i or negedge arstn_i) begin + if (!arstn_i) an_ff <= ~8'b1; + else if (an_en) an_ff <= an_next; + end + + Semseg current_semseg; + always_comb begin + unique case (1'b0) + an_ff[0]: current_semseg = all_semsegs_i[7]; + an_ff[1]: current_semseg = all_semsegs_i[6]; + an_ff[2]: current_semseg = all_semsegs_i[5]; + an_ff[3]: current_semseg = all_semsegs_i[4]; + an_ff[4]: current_semseg = all_semsegs_i[3]; + an_ff[5]: current_semseg = all_semsegs_i[2]; + an_ff[6]: current_semseg = all_semsegs_i[1]; + an_ff[7]: current_semseg = all_semsegs_i[0]; + endcase + end + + assign current_semseg_o = current_semseg; + + assign an_o = an_ff; + +endmodule + +module debounce #( + parameter int unsigned MAX_COUNT = 10000 +) ( + input logic clk_i, + input logic arstn_i, + input logic data_i, + output logic data_o +); + + localparam int COUNTER_WIDTH = $clog2(MAX_COUNT); + logic [COUNTER_WIDTH-1:0] counter_next; + logic [COUNTER_WIDTH-1:0] counter_ff; + assign counter_next = (data_o != data_i) ? counter_ff - COUNTER_WIDTH'('b1) : + COUNTER_WIDTH'(MAX_COUNT); + always_ff @(posedge clk_i or negedge arstn_i) begin + if (!arstn_i) counter_ff <= COUNTER_WIDTH'(MAX_COUNT); + else counter_ff <= counter_next; + end + + always_ff @(posedge clk_i or negedge arstn_i) begin + if (!arstn_i) data_o <= '0; + else if (~|counter_ff) data_o <= data_i; end endmodule + +module sync #( + parameter int unsigned SYNC_STAGES = 3 +) ( + input logic clk_i, + input logic data_i, + output logic data_o +); + + logic [SYNC_STAGES-1:0] sync_buffer_ff; + logic [SYNC_STAGES-1:0] sync_buffer_next; + assign sync_buffer_next = {sync_buffer_ff[$left(sync_buffer_ff)-1:0], data_i}; + always_ff @(posedge clk_i) begin + sync_buffer_ff <= sync_buffer_next; + end + + assign data_o = sync_buffer_ff[$left(sync_buffer_ff)]; + +endmodule diff --git a/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv b/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv deleted file mode 100644 index 91c83e3..0000000 --- a/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv +++ /dev/null @@ -1,85 +0,0 @@ -/* ----------------------------------------------------------------------------- -* Project Name : Architectures of Processor Systems (APS) lab work -* Organization : National Research University of Electronic Technology (MIET) -* Department : Institute of Microdevices and Control Systems -* Author(s) : Nikita Bulavin -* Email(s) : nekkit6@edu.miet.ru - -See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. -* ------------------------------------------------------------------------------ -*/ -module nexys_CYBERcobra( - input CLK100, - input resetn, - input BTND, - input [15:0] SW, - output CA, CB, CC, CD, CE, CF, CG, - output [7:0] AN - ); - - CYBERcobra dut( - .clk_i(CLK100), - .rst_i(!resetn), - .sw_i({7'b0,splash,SW[7:0]}), - .out_o(out) - ); - -localparam pwm = 1000; -reg [9:0] counter; -reg [3:0] semseg; -reg [7:0] ANreg; -reg CAr, CBr, CCr, CDr, CEr, CFr, CGr; -reg [3:0] btn; -reg [10:0] btn_reg; -wire splash; -wire [31:0] out; - -assign AN[7:0] = ANreg[7:0]; -assign {CA, CB, CC, CD, CE, CF, CG} = {CAr, CBr, CCr, CDr, CEr, CFr, CGr}; -assign splash = ((btn == 4'b1111) ^ btn_reg[10]) && (btn == 4'b1111); - -always @(posedge CLK100) begin - if (!resetn) begin - counter <= 'b0; - ANreg[7:0] <= 8'b11111111; - {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; - btn <= 4'b0; - btn_reg <= 0; - end - else begin - btn <= (btn << 1'b1) + BTND; - btn_reg <= (btn_reg << 1'b1) + (btn == 4'b1111); - if (counter < pwm) counter = counter + 'b1; - else begin - counter = 'b0; - ANreg[1] <= ANreg[0]; - ANreg[2] <= ANreg[1]; - ANreg[3] <= ANreg[2]; - ANreg[4] <= ANreg[3]; - ANreg[5] <= ANreg[4]; - ANreg[6] <= ANreg[5]; - ANreg[7] <= ANreg[6]; - ANreg[0] <= !(ANreg[6:0] == 7'b1111111); - end - case (1'b0) - ANreg[0]: semseg <= out[3 : 0]; - ANreg[1]: semseg <= out[7 : 4]; - ANreg[2]: semseg <= out[11: 8]; - ANreg[3]: semseg <= out[15:12]; - ANreg[4]: semseg <= out[19:16]; - ANreg[5]: semseg <= out[23:20]; - ANreg[6]: semseg <= out[27:24]; - ANreg[7]: semseg <= out[31:28]; - endcase - case (semseg) - 4'h1: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //L - 4'h3: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110110; //? - 4'h8: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; //O - 4'hA: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; //A - 4'hC: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001000; //H - default: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; // - endcase - end - end - -endmodule