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ЛР15. Хотфиксы
This commit is contained in:
Andrei Solodovnikov
@@ -572,8 +572,8 @@ _Листинг 6. Пример использования скрипта для
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4. [Реализуйте](#реализация-интерфейсов-памяти-инструкций-и-данных) интерфейсы памяти инструкций и данных.
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5. [Реализуйте](#реализация-оставшейся-части-логики) логику оставшихся сигналов.
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4. После описания модуля, его необходимо проверить с помощью тестового окружения.
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1. Тестбенч находится [здесь](tb_bluster.sv).
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2. Для работы тестбенча потребуется потребуется пакет [`peripheral_pkg`](../13.%20Peripheral%20units/peripheral_pkg.sv) из ЛР№13.
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1. Тестбенч находится [здесь](lab_15_tb_bluster.sv).
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2. Для работы тестбенча потребуется потребуется пакет [`peripheral_pkg`](../13.%20Peripheral%20units/peripheral_pkg.sv) из ЛР№13, а также файлы [`lab_15_char.mem`](lab_15_char.mem), [`lab_15_data.mem`](lab_15_data.mem), [`lab_15_instr.mem`](lab_15_instr.mem) из папки [mem_files](mem_files).
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3. Перед запуском симуляции убедитесь, что в качестве top-level модуля выбран корректный (`lab_15_tb_bluster`).
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4. Для запуска симуляции воспользуйтесь [`этой инструкцией`](../../Vivado%20Basics/Run%20Simulation.md).
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5. **По завершению симуляции убедитесь, что в логе есть сообщение о завершении теста!**
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@@ -586,11 +586,11 @@ _Листинг 6. Пример использования скрипта для
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3. Замените сигнал сброса модуля `riscv_core` сигналом `core_reset_o`.
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4. В случае если у вас есть периферийное устройство `uart_tx` его выход `tx_o` необходимо мультиплексировать с выходом `tx_o` программатора аналогично тому, как был мультиплексирован интерфейс памяти данных.
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6. После интеграции модуля, его необходимо проверить с помощью тестового окружения.
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1. Тестовое окружение находится [здесь](tb_top_asic.sv).
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1. Тестовое окружение находится [здесь](lab_15_tb_system.sv).
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1. Данный тестбенч необходимо обновить под свой вариант. Найдите строки со вспомогательным вызовом `program_region`, первыми аргументами которого являются "YOUR_INSTR_MEM_FILE" и "YOUR_DATA_MEM_FILE". Обновите эти строки под имена файлов, которыми вы инициализировали свои память инструкций и данных в ЛР№13. Если память данных вы не инициализировали, можете удалить/закомментировать соответствующий вызов. При необходимости вы можете добавить столько вызовов, сколько вам потребуется.
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2. В .mem-файлах, которыми вы будете инициализировать вашу память необходимо сделать доработку. Вам необходимо указать адрес ячейки памяти, с которой необходимо начать инициализировать память. Это делается путем добавления в начало файла строки вида: `@hex_address`. Пример `@FA000000`. Строка обязательно должна начинаться с символа `@`, а адрес обязательно должен быть в шестнадцатеричном виде. Для памяти инструкций нужен нулевой адрес, а значит можно использовать строку `@00000000`. Для памяти данных необходимо адрес, превышающий размер памяти инструкций, но не попадающий в адресное пространство других периферийных устройств (старший байт адреса должен быть равен нулю). Поскольку система использует байтовую адресацию, адрес ячеек будет в 4 раза меньше адреса по которому обратился бы процессор. Это значит, что если бы вы хотели проинициализировать память VGA-контроллера, вам нужно было бы использовать не адрес `@07000000`, а `@01C00000` (`01C00000 * 4 = 07000000`). Таким образом, для памяти данных оптимальным адресом инициализации будет `@00200000`, поскольку эта ячейка с адресом `00200000` соответствует адресу `00800000` — этот адрес не накладывается на адресное пространство других периферийных устройств, но при этом заведомо больше возможного размера памяти инструкций.
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2. В .mem-файлах, которыми вы будете инициализировать вашу память необходимо сделать доработку. Вам необходимо указать адрес ячейки памяти, с которой необходимо начать инициализировать память. Это делается путем добавления в начало файла строки вида: `@hex_address`. Пример `@FA000000`. Строка обязательно должна начинаться с символа `@`, а адрес обязательно должен быть в шестнадцатеричном виде. Для памяти инструкций нужен нулевой адрес, а значит можно использовать строку `@00000000`. Для памяти данных необходимо адрес, превышающий размер памяти инструкций, но не попадающий в адресное пространство других периферийных устройств (старший байт адреса должен быть равен нулю). Поскольку система использует байтовую адресацию, адрес ячеек будет в 4 раза меньше адреса по которому обратился бы процессор. Это значит, что если бы вы хотели проинициализировать память VGA-контроллера, вам нужно было бы использовать не адрес `@07000000`, а `@01C00000` (`01C00000 * 4 = 07000000`). Таким образом, для памяти данных оптимальным адресом инициализации будет `@00200000`, поскольку эта ячейка с адресом `00200000` соответствует адресу `00800000` — этот адрес не накладывается на адресное пространство других периферийных устройств, но при этом заведомо больше возможного размера памяти инструкций. Примеры использования начальных адресов вы можете посмотреть в файлах [`lab_15_char.mem`](lab_15_char.mem), [`lab_15_data.mem`](lab_15_data.mem), [`lab_15_instr.mem`](lab_15_instr.mem) из папки [mem_files](mem_files).
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3. Тестбенч будет ожидать завершения инициализации памяти, после чего сформирует те же тестовые воздействия, что и в тестбенче к ЛР№13. А значит, если вы использовали для инициализации те же самые файлы, поведение вашей системы после инициализации не должно отличаться от поведения на симуляции в ЛР№13.
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2. Перед запуском симуляции убедитесь, что в качестве top-level модуля выбран корректный (`tb_top_asic`).
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2. Перед запуском симуляции убедитесь, что в качестве top-level модуля выбран корректный (`lab_15_tb_system`).
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3. Для запуска симуляции воспользуйтесь [`этой инструкцией`](../../Vivado%20Basics/Run%20Simulation.md).
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4. **По завершению симуляции убедитесь, что в логе есть сообщение о завершении теста!**
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7. Переходить к следующему пункту можно только после того, как вы полностью убедились в работоспособности системы на этапе моделирования (увидели, что в память инструкций и данных были записаны корректные данные, после чего процессор стал обрабатывать прерывания от устройства ввода). Генерация битстрима будет занимать у вас долгое время, а итогом вы получите результат: заработало / не заработало, без какой-либо дополнительной информации, поэтому без прочного фундамента на моделировании далеко уехать у вас не выйдет.
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@@ -598,7 +598,7 @@ _Листинг 6. Пример использования скрипта для
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9. Проверьте работу вашей процессорной системы на отладочном стенде с ПЛИС.
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1. Для инициализации памяти процессорной системы используется скрипт [flash.py](flash.py).
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2. Перед инициализацией необходимо подключить отладочный стенд к последовательному порту компьютера и узнать номер этого порта (см. [пример загрузки программы](#пример-загрузки-программы)).
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3. Формат файлов для инициализации памяти с помощью скрипта аналогичен формату, использовавшемуся в [тестбенче](tb_top_asic.sv). Это значит что первой строчкой всех файлов должна быть строка, содержащая адрес ячейки памяти, с которой должна начаться инициализация (см. п. 5.1.2).
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3. Формат файлов для инициализации памяти с помощью скрипта аналогичен формату, использовавшемуся в [тестбенче](lab_15_tb_bluster.sv). Это значит что первой строчкой всех файлов должна быть строка, содержащая адрес ячейки памяти, с которой должна начаться инициализация (см. п. 5.1.2).
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## Список источников
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113
Labs/15. Programming device/bluster_pkg.sv
Normal file
113
Labs/15. Programming device/bluster_pkg.sv
Normal file
@@ -0,0 +1,113 @@
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/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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package bluster_pkg;
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localparam INIT_MSG_SIZE = 41;
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localparam FLASH_MSG_SIZE = 57;
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localparam ACK_MSG_SIZE = 4;
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/* -----------------------------------------------------------------------------
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Lab_15 tb tasks
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* -----------------------------------------------------------------------------
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*/
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task automatic send_data(input byte mem[$], ref logic clk_i, tx_valid, tx_busy, ref logic [7:0] tx_data);
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for(int i = mem.size()-1; i >=0; i--) begin
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tx_data = mem[i];
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tx_valid = 1'b1;
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@(posedge clk_i);
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tx_valid = 1'b0;
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@(posedge clk_i);
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while(tx_busy) @(posedge clk_i);
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end
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endtask
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task automatic rcv_data(input int size, ref logic clk_i, rx_valid, tx_o, ref logic [7:0] rx_data);
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automatic logic [0:FLASH_MSG_SIZE-1][7:0] str;
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automatic logic [3:0][7:0] size_val;
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for(int i = 0; i < size; i++) begin
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@(posedge clk_i);
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while(!rx_valid)@(posedge clk_i);
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str[i] = rx_data;
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size_val[3-i] = rx_data;
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end
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case(size)
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INIT_MSG_SIZE: begin
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$display("%s", str[0:INIT_MSG_SIZE-2]);
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assert(str[0:INIT_MSG_SIZE-10] == "ready for flash starting from 0x")begin end
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else $error("Init message format is incorrect. Should be \"ready for flash starting from 0xADDR\"");
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end
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FLASH_MSG_SIZE: begin
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$display("%s", str[0:FLASH_MSG_SIZE-2]);
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assert((str[0:16] == "finished write 0x") && (str[25+:23] == " bytes starting from 0x"))begin end
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else $error("finish message format is incorrect. Should be \"finished write 0xSIZE bytes starting from 0xADDR\"");
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end
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ACK_MSG_SIZE : $display("%0d", size_val);
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endcase
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wait(tx_o);
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endtask
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task automatic program_region(input string fname, ref logic clk_i, tx_valid, rx_valid, tx_o, tx_busy, reset, ref logic [7:0] rx_data, tx_data);
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automatic int fd, start_addr;
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automatic logic [31:0] data;
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automatic byte mem[$];
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automatic byte str [4];
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automatic logic [3:0][7:0] size;
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$display("\n%0t. Start programming %s", $time, fname);
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fd = $fopen(fname, "r");
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assert(fd)
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else $fatal(1, "Can't open file %s", fname);
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void'($fscanf(fd, "@%x\w", start_addr));
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start_addr <<=2;
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while(!$feof(fd)) begin
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$fscanf(fd, "%x\w", data);
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mem.push_back(data[ 7: 0]);
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mem.push_back(data[15: 8]);
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mem.push_back(data[23:16]);
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mem.push_back(data[31:24]);
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end
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$fclose(fd);
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size = mem.size();
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str = {start_addr[7:0],start_addr[15:8],start_addr[23:16],start_addr[31:24]};
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send_data(str, clk_i, tx_valid, tx_busy, tx_data);
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rcv_data(INIT_MSG_SIZE, clk_i, rx_valid, tx_o, rx_data);
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str = {size[0],size[1],size[2],size[3]};
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send_data(str, clk_i, tx_valid, tx_busy, tx_data);
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rcv_data(ACK_MSG_SIZE, clk_i, rx_valid, tx_o, rx_data);
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send_data(mem, clk_i, tx_valid, tx_busy, tx_data);
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rcv_data(FLASH_MSG_SIZE, clk_i, rx_valid, tx_o, rx_data);
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$display("%0t. Region has been programmed", $time);
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assert(reset)
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else $error("Reset must be equal 1 while flashing is not done.");
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endtask
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task automatic finish_programming(ref logic clk_i, tx_valid, tx_busy, reset, ref logic [7:0] tx_data);
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automatic byte mem[$];
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mem.push_back(8'hff);
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mem.push_back(8'hff);
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mem.push_back(8'hff);
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mem.push_back(8'hff);
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send_data(mem, clk_i, tx_valid, tx_busy, tx_data);
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$display("Flashing is complete");
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assert(!reset)
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else $error("Reset must be equal 0 after flashing is complete.");
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endtask
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task automatic dummy_programming(ref logic clk_i, tx_valid, rx_valid, tx_o, tx_busy, reset, ref logic [7:0] rx_data, tx_data);
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automatic byte str [4] = {8'd0, 8'd0, 8'd0, 8'd0};
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rcv_data(INIT_MSG_SIZE, clk_i, rx_valid, tx_o, rx_data);
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send_data(str, clk_i, tx_valid, tx_busy, tx_data);
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rcv_data(ACK_MSG_SIZE, clk_i, rx_valid, tx_o, rx_data);
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rcv_data(FLASH_MSG_SIZE, clk_i, rx_valid, tx_o, rx_data);
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finish_programming(clk_i, tx_valid, tx_busy, reset, rx_data);
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endtask
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endpackage
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111
Labs/15. Programming device/lab_15.tb_bluster.sv
Normal file
111
Labs/15. Programming device/lab_15.tb_bluster.sv
Normal file
@@ -0,0 +1,111 @@
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/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module lab_15_tb_bluster();
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logic clk_i;
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logic rst_i;
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logic rx_i;
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logic tx_o;
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logic [ 31:0] instr_addr_o;
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logic [ 31:0] instr_wdata_o;
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logic instr_we_o;
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logic [ 31:0] data_addr_o;
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logic [ 31:0] data_wdata_o;
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logic data_we_o;
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logic core_reset_o;
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logic rx_busy, rx_valid, tx_busy, tx_valid;
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logic [7:0] rx_data, tx_data;
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logic [31:0] instr_addr_i;
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logic [31:0] instr_rdata_o;
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import bluster_pkg::*;
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byte init_str[INIT_MSG_SIZE];
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byte done_str[FLASH_MSG_SIZE];
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always #50ns clk_i = !clk_i;
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initial begin
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$timeformat(-9, 2, " ns", 3);
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clk_i = 0;
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rst_i <= 0;
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@(posedge clk_i);
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rst_i <= 1;
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repeat(2) @(posedge clk_i);
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rst_i <= 0;
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program_region("lab_15_instr.mem", clk_i, tx_valid, rx_valid, tx_o, tx_busy, core_reset_o, rx_data, tx_data);
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program_region("lab_15_data.mem", clk_i, tx_valid, rx_valid, tx_o, tx_busy, core_reset_o, rx_data, tx_data);
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program_region("lab_15_char.mem", clk_i, tx_valid, rx_valid, tx_o, tx_busy, core_reset_o, rx_data, tx_data);
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finish_programming(clk_i, tx_valid, tx_busy, core_reset_o, tx_data);
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$finish();
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end
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bluster blust(.*);
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uart_rx rx(
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.clk_i (clk_i ),
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.rst_i (rst_i ),
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.rx_i (tx_o ),
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.busy_o (rx_busy ),
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.baudrate_i (17'd115200 ),
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.parity_en_i(1'b1 ),
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.stopbit_i (2'b1 ),
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.rx_data_o (rx_data ),
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.rx_valid_o (rx_valid )
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);
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uart_tx tx(
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.clk_i (clk_i ),
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.rst_i (rst_i ),
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.tx_o (rx_i ),
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.busy_o (tx_busy ),
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.baudrate_i (17'd115200 ),
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.parity_en_i(1'b1 ),
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.stopbit_i (2'b1 ),
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.tx_data_i (tx_data ),
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.tx_valid_i (tx_valid )
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);
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rw_instr_mem imem(
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.clk_i (clk_i ) ,
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.read_addr_i (instr_addr_i ) ,
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.read_data_o (instr_rdata_o ) ,
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.write_addr_i (instr_addr_o ) ,
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.write_data_i (instr_wdata_o ) ,
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.write_enable_i(instr_we_o )
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);
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data_mem dmem(
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.clk_i (clk_i ),
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.mem_req_i (data_addr_o[31:24] == 0),
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.write_enable_i (data_we_o ),
|
||||
.byte_enable_i (4'b1111 ),
|
||||
.addr_i (data_addr_o ),
|
||||
.write_data_i (data_wdata_o ),
|
||||
.read_data_o (),
|
||||
.ready_o ()
|
||||
);
|
||||
|
||||
data_mem cmem(
|
||||
.clk_i (clk_i ),
|
||||
.mem_req_i (data_addr_o[31:24] == 7),
|
||||
.write_enable_i (data_we_o ),
|
||||
.byte_enable_i (4'b1111 ),
|
||||
.addr_i (data_addr_o ),
|
||||
.write_data_i (data_wdata_o ),
|
||||
.read_data_o (),
|
||||
.ready_o ()
|
||||
);
|
||||
|
||||
endmodule
|
||||
140
Labs/15. Programming device/lab_15.tb_system.sv
Normal file
140
Labs/15. Programming device/lab_15.tb_system.sv
Normal file
@@ -0,0 +1,140 @@
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Project Name : Architectures of Processor Systems (APS) lab work
|
||||
* Organization : National Research University of Electronic Technology (MIET)
|
||||
* Department : Institute of Microdevices and Control Systems
|
||||
* Author(s) : Andrei Solodovnikov
|
||||
* Email(s) : hepoh@org.miet.ru
|
||||
|
||||
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
|
||||
* ------------------------------------------------------------------------------
|
||||
*/
|
||||
module lab_15_tb_system();
|
||||
|
||||
logic clk_i;
|
||||
logic sysclk;
|
||||
logic rst_i;
|
||||
logic flash_rx;
|
||||
logic tx_o;
|
||||
logic ps2_clk, ps2_dat;
|
||||
logic sw_i;
|
||||
logic tb_rx;
|
||||
logic flashing_is_done = 0;
|
||||
logic core_reset;
|
||||
|
||||
logic rx_busy, rx_valid, tx_busy, tx_valid;
|
||||
logic [7:0] rx_data, tx_data;
|
||||
|
||||
import bluster_pkg::*;
|
||||
import peripheral_pkg::*;
|
||||
|
||||
byte init_str[INIT_MSG_SIZE];
|
||||
byte done_str[FLASH_MSG_SIZE];
|
||||
|
||||
always #5ns clk_i = !clk_i;
|
||||
always #50ns sysclk = !sysclk;
|
||||
|
||||
initial begin
|
||||
$timeformat(-9, 2, " ns", 3);
|
||||
sysclk = 0;
|
||||
clk_i = 0;
|
||||
rst_i <= 0;
|
||||
@(posedge sysclk);
|
||||
rst_i <= 1;
|
||||
repeat(2) @(posedge sysclk);
|
||||
rst_i <= 0;
|
||||
program_region("YOUR_INSTR_MEM_FILE.mem", sysclk, tx_valid, rx_valid, tx_o, tx_busy, core_reset, rx_data, tx_data);
|
||||
program_region("YOUR_DATA_MEM_FILE.mem", sysclk, tx_valid, rx_valid, tx_o, tx_busy, core_reset, rx_data, tx_data);
|
||||
finish_programming(sysclk, tx_valid, tx_busy, core_reset, tx_data);
|
||||
repeat(200) @(posedge sysclk);
|
||||
flashing_is_done = 1;
|
||||
#4ms;
|
||||
$finish();
|
||||
end
|
||||
|
||||
initial begin: sw_block
|
||||
sw_i = 16'd0;
|
||||
wait(flashing_is_done);
|
||||
sw_i = 16'hdead;
|
||||
repeat(1000) @(posedge clk_i);
|
||||
sw_i = 16'h5555;
|
||||
repeat(1000) @(posedge clk_i);
|
||||
sw_i = 16'hbeef;
|
||||
repeat(1000) @(posedge clk_i);
|
||||
sw_i = 16'haaaa;
|
||||
end
|
||||
|
||||
initial begin: ps2_initial_block
|
||||
ps2_clk = 1'b1;
|
||||
ps2_dat = 1'b1;
|
||||
wait(flashing_is_done);
|
||||
ps2_send_scan_code(8'h1C, ps2_clk, ps2_dat);
|
||||
repeat(1000) @(posedge clk_i);
|
||||
ps2_send_scan_code(8'hf0, ps2_clk, ps2_dat);
|
||||
repeat(1000) @(posedge clk_i);
|
||||
ps2_send_scan_code(8'h1C, ps2_clk, ps2_dat);
|
||||
repeat(1000) @(posedge clk_i);
|
||||
ps2_send_scan_code(8'h32, ps2_clk, ps2_dat);
|
||||
repeat(1000) @(posedge clk_i);
|
||||
ps2_send_scan_code(8'hf0, ps2_clk, ps2_dat);
|
||||
repeat(1000) @(posedge clk_i);
|
||||
ps2_send_scan_code(8'h32, ps2_clk, ps2_dat);
|
||||
repeat(1000) @(posedge clk_i);
|
||||
ps2_send_scan_code(8'h21, ps2_clk, ps2_dat);
|
||||
repeat(1000) @(posedge clk_i);
|
||||
ps2_send_scan_code(8'hf0, ps2_clk, ps2_dat);
|
||||
repeat(1000) @(posedge clk_i);
|
||||
ps2_send_scan_code(8'h21, ps2_clk, ps2_dat);
|
||||
end
|
||||
|
||||
initial begin: uart_rx_initial_block
|
||||
tb_rx = 1'b1;
|
||||
wait(flashing_is_done);
|
||||
uart_rx_send_char(8'h1c, 115200, tb_rx);
|
||||
repeat(1000) @(posedge clk_i);
|
||||
uart_rx_send_char(8'h0D, 115200, tb_rx);
|
||||
repeat(1000) @(posedge clk_i);
|
||||
uart_rx_send_char(8'h0D, 115200, tb_rx);
|
||||
repeat(1000) @(posedge clk_i);
|
||||
uart_rx_send_char(8'h7F, 115200, tb_rx);
|
||||
repeat(1000) @(posedge clk_i);
|
||||
uart_rx_send_char(8'h7F, 115200, tb_rx);
|
||||
end
|
||||
|
||||
|
||||
system dut(
|
||||
.clk_i (clk_i ),
|
||||
.resetn_i (!rst_i ),
|
||||
.rx_i (flashing_is_done ? tb_rx : flash_rx ),
|
||||
.tx_o (tx_o ),
|
||||
.kclk_i (ps2_clk),
|
||||
.kdata_i (ps2_dat),
|
||||
.sw_i (sw_i )
|
||||
);
|
||||
|
||||
assign core_reset = dut.core_inst.rst_i;
|
||||
|
||||
uart_rx rx(
|
||||
.clk_i (sysclk ),
|
||||
.rst_i (rst_i ),
|
||||
.rx_i (tx_o ),
|
||||
.busy_o (rx_busy ),
|
||||
.baudrate_i (17'd115200 ),
|
||||
.parity_en_i(1'b1 ),
|
||||
.stopbit_i (2'b1 ),
|
||||
.rx_data_o (rx_data ),
|
||||
.rx_valid_o (rx_valid )
|
||||
);
|
||||
|
||||
uart_tx tx(
|
||||
.clk_i (sysclk ),
|
||||
.rst_i (rst_i ),
|
||||
.tx_o (flash_rx ),
|
||||
.busy_o (tx_busy ),
|
||||
.baudrate_i (17'd115200 ),
|
||||
.parity_en_i(1'b1 ),
|
||||
.stopbit_i (2'b1 ),
|
||||
.tx_data_i (tx_data ),
|
||||
.tx_valid_i (tx_valid )
|
||||
);
|
||||
|
||||
endmodule
|
||||
10
Labs/15. Programming device/mem_files/lab_15_char.mem
Normal file
10
Labs/15. Programming device/mem_files/lab_15_char.mem
Normal file
@@ -0,0 +1,10 @@
|
||||
@01C00000
|
||||
20202020
|
||||
20202020
|
||||
20202020
|
||||
20202020
|
||||
20202020
|
||||
20202020
|
||||
20202020
|
||||
20202020
|
||||
20202020
|
||||
24
Labs/15. Programming device/mem_files/lab_15_data.mem
Normal file
24
Labs/15. Programming device/mem_files/lab_15_data.mem
Normal file
@@ -0,0 +1,24 @@
|
||||
@00200000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
007E0900
|
||||
00000000
|
||||
00317100
|
||||
737A0000
|
||||
00327761
|
||||
64786300
|
||||
00333465
|
||||
66762000
|
||||
00357274
|
||||
68626E00
|
||||
00367967
|
||||
6A6D0000
|
||||
00383775
|
||||
696B2C00
|
||||
0039306F
|
||||
6C2F2E00
|
||||
002D703B
|
||||
00270000
|
||||
00003D5B
|
||||
5D0D0000
|
||||
18
Labs/15. Programming device/mem_files/lab_15_instr.mem
Normal file
18
Labs/15. Programming device/mem_files/lab_15_instr.mem
Normal file
@@ -0,0 +1,18 @@
|
||||
@00000000
|
||||
030000b7
|
||||
00008093
|
||||
07000137
|
||||
00010113
|
||||
07001337
|
||||
96030313
|
||||
0040a383
|
||||
fe038ee3
|
||||
0000a183
|
||||
00018203
|
||||
00410023
|
||||
00110113
|
||||
00615463
|
||||
fe5ff06f
|
||||
07000137
|
||||
00010113
|
||||
fd9ff06f
|
||||
@@ -1,563 +0,0 @@
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Project Name : Architectures of Processor Systems (APS) lab work
|
||||
* Organization : National Research University of Electronic Technology (MIET)
|
||||
* Department : Institute of Microdevices and Control Systems
|
||||
* Author(s) : Andrei Solodovnikov
|
||||
* Email(s) : hepoh@org.miet.ru
|
||||
|
||||
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
|
||||
* ------------------------------------------------------------------------------
|
||||
*/
|
||||
module tb_blaster();
|
||||
|
||||
logic clk_i;
|
||||
logic rst_i;
|
||||
logic rx_i;
|
||||
logic tx_o;
|
||||
logic [ 31:0] instr_addr_o;
|
||||
logic [ 31:0] instr_wdata_o;
|
||||
logic instr_write_enable_o;
|
||||
logic [ 31:0] data_addr_o;
|
||||
logic [ 31:0] data_wdata_o;
|
||||
logic data_write_enable_o;
|
||||
logic [ 31:0] tiff_addr_o;
|
||||
logic [127:0] tiff_wdata_o;
|
||||
logic tiff_write_enable_o;
|
||||
logic core_reset_o;
|
||||
|
||||
logic rx_busy, rx_valid, tx_busy, tx_valid;
|
||||
logic [7:0] rx_data, tx_data;
|
||||
|
||||
logic [31:0] instr_addr_i;
|
||||
logic [31:0] instr_rdata_o;
|
||||
logic [31:0] tiff_addr_i;
|
||||
logic [127:0] tiff_rdata_o;
|
||||
|
||||
logic [3:0] [7:0] flash_addr;
|
||||
logic [3:0] [7:0] instr_size;
|
||||
logic [3:0] [7:0] instr_size_ack;
|
||||
logic [3:0] [7:0] data_size;
|
||||
logic [3:0] [7:0] data_size_ack;
|
||||
logic [3:0] [7:0] tiff_size;
|
||||
logic [3:0] [7:0] tiff_size_ack;
|
||||
|
||||
logic [7:0] instr_mem_byte[$];
|
||||
logic [7:0] data_mem_byte[$];
|
||||
logic [7:0] tiff_mem_byte [$];
|
||||
|
||||
localparam INIT_MSG_SIZE = 40;
|
||||
localparam MSG_DONE_SIZE = 57;
|
||||
localparam MSG_ACK_SIZE = 4;
|
||||
|
||||
byte init_str[INIT_MSG_SIZE];
|
||||
byte done_str[MSG_DONE_SIZE];
|
||||
|
||||
always #50ns clk_i = !clk_i;
|
||||
|
||||
initial begin
|
||||
$timeformat(-9, 2, " ns", 3);
|
||||
clk_i = 0;
|
||||
rst_i <= 0;
|
||||
@(posedge clk_i);
|
||||
rst_i <= 1;
|
||||
repeat(2) @(posedge clk_i);
|
||||
rst_i <= 0;
|
||||
instr_size = instr_mem_byte.size();
|
||||
data_size = data_mem_byte.size();
|
||||
tiff_size = tiff_mem_byte.size();
|
||||
|
||||
/*
|
||||
RCV_NEXT_COMMAND
|
||||
*/
|
||||
flash_addr = 32'h0000;
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = flash_addr[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
|
||||
/*
|
||||
INIT_MSG
|
||||
*/
|
||||
for(int i = 0; i < INIT_MSG_SIZE; i++) begin
|
||||
@(posedge clk_i);
|
||||
while(!rx_valid)@(posedge clk_i);
|
||||
init_str[i] = rx_data;
|
||||
end
|
||||
$display("%s", init_str);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
repeat(10000)@(posedge clk_i);
|
||||
|
||||
/*
|
||||
RCV_INSTR_SIZE
|
||||
*/
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = instr_size[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
INSTR_SIZE_ACK
|
||||
*/
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
while(!rx_valid) @(posedge clk_i);
|
||||
instr_size_ack[i] = rx_data;
|
||||
@(posedge clk_i);
|
||||
end
|
||||
$display("%h", instr_size);
|
||||
assert(instr_size_ack == instr_size)
|
||||
else $error("ack: %0h, size: %0h", instr_size_ack, instr_size);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
|
||||
/*
|
||||
INSTR_FLASH
|
||||
*/
|
||||
if(instr_size)repeat(10000)@(posedge clk_i);
|
||||
for(int i = instr_size-1; i >=0; i--) begin
|
||||
tx_data = instr_mem_byte[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
INSTR_FLASH_ACK
|
||||
*/
|
||||
for(int i = 0; i < MSG_DONE_SIZE; i++) begin
|
||||
@(posedge clk_i);
|
||||
while(!rx_valid)@(posedge clk_i);
|
||||
done_str[i] = rx_data;
|
||||
end
|
||||
$display("%t %s", $time, done_str);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
|
||||
repeat(10000)@(posedge clk_i);
|
||||
|
||||
/*
|
||||
RCV_NEXT_COMMAND
|
||||
*/ flash_addr = 32'h4000;
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = flash_addr[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
|
||||
|
||||
/*
|
||||
INIT_MSG
|
||||
*/
|
||||
for(int i = 0; i < INIT_MSG_SIZE; i++) begin
|
||||
@(posedge clk_i);
|
||||
while(!rx_valid)@(posedge clk_i);
|
||||
init_str[i] = rx_data;
|
||||
end
|
||||
$display("%s", init_str);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
/*
|
||||
RCV_DATA_SIZE
|
||||
*/
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = data_size[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
DATA_SIZE_ACK
|
||||
*/
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
while(!rx_valid) @(posedge clk_i);
|
||||
data_size_ack[i] = rx_data;
|
||||
@(posedge clk_i);
|
||||
end
|
||||
$display("%h", data_size);
|
||||
assert(data_size_ack == data_size)
|
||||
else $error("ack: %0h, size: %0h", data_size_ack, data_size);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
DATA_FLASH
|
||||
*/
|
||||
if(data_size)repeat(10000)@(posedge clk_i);
|
||||
for(int i = data_size-1; i >=0; i--) begin
|
||||
tx_data = data_mem_byte[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
DATA_FLASH_ACK
|
||||
*/
|
||||
for(int i = 0; i < MSG_DONE_SIZE; i++) begin
|
||||
@(posedge clk_i);
|
||||
while(!rx_valid)@(posedge clk_i);
|
||||
done_str[i] = rx_data;
|
||||
end
|
||||
$display("%t %s", $time, done_str);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
repeat(10000)@(posedge clk_i);
|
||||
|
||||
|
||||
/*
|
||||
RCV_NEXT_COMMAND
|
||||
*/ flash_addr = 32'h0800_0000;
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = flash_addr[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
|
||||
/*
|
||||
INIT_MSG
|
||||
*/
|
||||
for(int i = 0; i < INIT_MSG_SIZE; i++) begin
|
||||
@(posedge clk_i);
|
||||
while(!rx_valid)@(posedge clk_i);
|
||||
init_str[i] = rx_data;
|
||||
end
|
||||
$display("%s", init_str);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
/*
|
||||
RCV_TIFF_SIZE
|
||||
*/
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = tiff_size[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
TIFF_SIZE_ACK
|
||||
*/
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
while(!rx_valid) @(posedge clk_i);
|
||||
tiff_size_ack[i] = rx_data;
|
||||
@(posedge clk_i);
|
||||
end
|
||||
$display("%h", tiff_size);
|
||||
assert(tiff_size_ack == tiff_size)
|
||||
else $display("ack: %0h, size: %0h", tiff_size_ack, tiff_size);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
|
||||
/*
|
||||
TIFF_FLASH
|
||||
*/
|
||||
if(tiff_size)repeat(10000)@(posedge clk_i);
|
||||
for(int i = tiff_size-1; i >=0; i--) begin
|
||||
tx_data = tiff_mem_byte[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
TIFF_FLASH_ACK, FINISH
|
||||
*/
|
||||
for(int i = 0; i < MSG_DONE_SIZE; i++) begin
|
||||
@(posedge clk_i);
|
||||
while(!rx_valid)@(posedge clk_i);
|
||||
done_str[i] = rx_data;
|
||||
end
|
||||
$display("%t %s", $time, done_str);
|
||||
wait(!rx_busy)
|
||||
@(posedge clk_i)
|
||||
|
||||
/*
|
||||
RCV_NEXT_COMMAND
|
||||
*/ flash_addr = 32'hFFFF_FFFF;
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = flash_addr[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
|
||||
assert(!core_reset_o)
|
||||
else $error("reset is not equal zero at the end");
|
||||
// ----------------------------------------------
|
||||
|
||||
repeat(10000)@(posedge clk_i);
|
||||
|
||||
$finish();
|
||||
end
|
||||
|
||||
|
||||
bluster blust(.*);
|
||||
|
||||
uart_rx rx(
|
||||
.clk_i (clk_i ),
|
||||
.rst_i (rst_i ),
|
||||
.rx_i (tx_o ),
|
||||
.busy_o (rx_busy ),
|
||||
.baudrate_i (17'd115200 ),
|
||||
.parity_en_i(1'b1 ),
|
||||
.stopbit_i (1'b1 ),
|
||||
.rx_data_o (rx_data ),
|
||||
.rx_valid_o (rx_valid )
|
||||
);
|
||||
|
||||
uart_tx tx(
|
||||
.clk_i (clk_i ),
|
||||
.rst_i (rst_i ),
|
||||
.tx_o (rx_i ),
|
||||
.busy_o (tx_busy ),
|
||||
.baudrate_i (17'd115200 ),
|
||||
.parity_en_i(1'b1 ),
|
||||
.stopbit_i (1'b1 ),
|
||||
.tx_data_i (tx_data ),
|
||||
.tx_valid_i (tx_valid )
|
||||
);
|
||||
|
||||
rw_instr_mem imem(
|
||||
.clk_i (clk_i ) ,
|
||||
.read_addr_i (instr_addr_i ) ,
|
||||
.read_data_o (instr_rdata_o ) ,
|
||||
.write_addr_i (instr_addr_o ) ,
|
||||
.write_data_i (instr_wdata_o ) ,
|
||||
.write_enable_i(instr_write_enable_o)
|
||||
);
|
||||
|
||||
ext_mem dmem(
|
||||
.clk_i (clk_i ),
|
||||
.mem_req_i (data_addr_o[31:24] == 0),
|
||||
.write_enable_i (data_write_enable_o),
|
||||
.byte_enable_i (4'b1111 ),
|
||||
.addr_i (data_addr_o ),
|
||||
.write_data_i (data_wdata_o ),
|
||||
.read_data_o (),
|
||||
.ready_o ()
|
||||
);
|
||||
|
||||
ext_mem tmem(
|
||||
.clk_i (clk_i ),
|
||||
.mem_req_i (data_addr_o[31:24] == 8),
|
||||
.write_enable_i (data_write_enable_o),
|
||||
.byte_enable_i (4'b1111 ),
|
||||
.addr_i (data_addr_o ),
|
||||
.write_data_i (data_wdata_o ),
|
||||
.read_data_o (),
|
||||
.ready_o ()
|
||||
);
|
||||
|
||||
initial instr_mem_byte = {
|
||||
8'h93, 8'h00, 8'h10, 8'h00, 8'h37, 8'h01, 8'h00, 8'h06, 8'hB7, 8'hC1, 8'h01, 8'h00, 8'h93, 8'h81, 8'h01, 8'h20,
|
||||
8'h23, 8'h26, 8'h31, 8'h00, 8'h13, 8'h02, 8'h10, 8'h00, 8'h23, 8'h28, 8'h41, 8'h00, 8'h93, 8'h02, 8'h10, 8'h00,
|
||||
8'h93, 8'h80, 8'h10, 8'h00, 8'h83, 8'h23, 8'h81, 8'h00, 8'h63, 8'h14, 8'h70, 8'h00, 8'h6F, 8'h00, 8'h00, 8'h00,
|
||||
8'h6F, 8'h00, 8'h00, 8'h00, 8'h23, 8'h20, 8'h11, 8'h00, 8'h6F, 8'h00, 8'h00, 8'h00
|
||||
};
|
||||
|
||||
initial #1 data_mem_byte = instr_mem_byte;
|
||||
|
||||
initial tiff_mem_byte = {
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000101, 8'b00000101, 8'b00000101, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00010010, 8'b00010010, 8'b00111111, 8'b00010010, 8'b00010010, 8'b00010010, 8'b00111111, 8'b00010010, 8'b00010010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000100, 8'b00001110, 8'b00010001, 8'b00010001, 8'b00000001, 8'b00001110, 8'b00010000, 8'b00010000, 8'b00010001, 8'b00010001, 8'b00001110, 8'b00000100, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000010, 8'b00000101, 8'b01000101, 8'b00100010, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00100010, 8'b01010001, 8'b01010000, 8'b00100000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00001100, 8'b00010010, 8'b00010010, 8'b00010010, 8'b01001100, 8'b01001010, 8'b00110001, 8'b00100001, 8'b00110001, 8'b01001110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000010, 8'b00000010, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000010, 8'b00000100, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000010, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00010010, 8'b00001100, 8'b00111111, 8'b00001100, 8'b00010010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000100, 8'b00000100, 8'b00011111, 8'b00000100, 8'b00000100, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000010, 8'b00000010, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00001111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00010000, 8'b00010000, 8'b00001000, 8'b00001000, 8'b00000100, 8'b00000100, 8'b00000010, 8'b00000010, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00110001, 8'b00101001, 8'b00101001, 8'b00100101, 8'b00100101, 8'b00100011, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00001000, 8'b00001100, 8'b00001010, 8'b00001001, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100000, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00000001, 8'b00111111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100000, 8'b00100000, 8'b00011100, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00010000, 8'b00011000, 8'b00010100, 8'b00010010, 8'b00010001, 8'b00111111, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00111111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00011111, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011100, 8'b00000010, 8'b00000001, 8'b00000001, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00111111, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111110, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000010, 8'b00000010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000010, 8'b00000010, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00000010, 8'b00000100, 8'b00001000, 8'b00010000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00111111, 8'b00000000, 8'b00111111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000001, 8'b00000010, 8'b00000100, 8'b00001000, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100000, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000000, 8'b00000100, 8'b00000100, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00111100, 8'b01000010, 8'b10011001, 8'b10100001, 8'b10111001, 8'b10100101, 8'b01111001, 8'b00000010, 8'b01111100, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00001111, 8'b00010001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00010001, 8'b00001111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00111111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00001111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00111111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00111111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00001111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00111001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100001, 8'b00100001, 8'b00010001, 8'b00001001, 8'b00000111, 8'b00001001, 8'b00010001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00111111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b01000001, 8'b01100011, 8'b01010101, 8'b01001001, 8'b01001001, 8'b01000001, 8'b01000001, 8'b01000001, 8'b01000001, 8'b01000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100001, 8'b00100011, 8'b00100101, 8'b00101001, 8'b00110001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00101001, 8'b00110001, 8'b00111110, 8'b00100000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011111, 8'b00010001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00000001, 8'b00000010, 8'b00001100, 8'b00010000, 8'b00100000, 8'b00100000, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b01111111, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b01000001, 8'b01000001, 8'b01000001, 8'b01000001, 8'b00100010, 8'b00100010, 8'b00010100, 8'b00010100, 8'b00001000, 8'b00001000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b01000001, 8'b01000001, 8'b01000001, 8'b01000001, 8'b01001001, 8'b01001001, 8'b01001001, 8'b01010101, 8'b01100011, 8'b01000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00010010, 8'b00001100, 8'b00001100, 8'b00010010, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b01000001, 8'b01000001, 8'b00100010, 8'b00100010, 8'b00010100, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00111111, 8'b00100000, 8'b00100000, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00000001, 8'b00111111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000111, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000010, 8'b00000010, 8'b00000100, 8'b00000100, 8'b00001000, 8'b00001000, 8'b00010000, 8'b00010000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000111, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000111, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000100, 8'b00001010, 8'b00010001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00111111, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00100000, 8'b00111110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00111110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00111111, 8'b00000001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011100, 8'b00100010, 8'b00000010, 8'b00000010, 8'b00001111, 8'b00000010, 8'b00000010, 8'b00000010, 8'b00000010, 8'b00000010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00110001, 8'b00101110, 8'b00100000, 8'b00100001, 8'b00011110, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000001, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00010000, 8'b00000000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010001, 8'b00010001, 8'b00001110, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00100001, 8'b00100001, 8'b00010001, 8'b00001111, 8'b00010001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00110111, 8'b01001001, 8'b01001001, 8'b01001001, 8'b01001001, 8'b01001001, 8'b01000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00111110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111110, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011101, 8'b00000011, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00000001, 8'b00011110, 8'b00100000, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000100, 8'b00000100, 8'b00011111, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00011000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b01000001, 8'b01000001, 8'b00100010, 8'b00100010, 8'b00010100, 8'b00010100, 8'b00001000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b01000001, 8'b01000001, 8'b01001001, 8'b01001001, 8'b01001001, 8'b01010101, 8'b00100010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b01000001, 8'b00100010, 8'b00010100, 8'b00001000, 8'b00010100, 8'b00100010, 8'b01000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00110001, 8'b00101110, 8'b00100000, 8'b00010000, 8'b00001111, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00111111, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00111111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011000, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000011, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00011000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000011, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00011000, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000011, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100110, 8'b00011001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000011, 8'b00000101, 8'b00000101, 8'b00000011, 8'b00000000, 8'b00001100, 8'b00001100, 8'b00000100, 8'b00101100, 8'b00100000, 8'b00100000, 8'b01100000, 8'b00000000, 8'b00000000, 8'b00000000
|
||||
};
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module rw_tiff_mem(
|
||||
input logic clk_i,
|
||||
input logic [ 31:0] addr_i,
|
||||
output logic [127:0] read_data_o,
|
||||
|
||||
input logic [ 31:0] write_addr_i,
|
||||
input logic [127:0] write_data_i,
|
||||
input logic write_enable_i
|
||||
);
|
||||
|
||||
logic [127:0] rom [256];
|
||||
|
||||
assign read_data_o = rom[addr_i];
|
||||
|
||||
always_ff @(posedge clk_i) begin
|
||||
if(write_enable_i) begin
|
||||
rom[write_addr_i] <= write_data_i;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,502 +0,0 @@
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Project Name : Architectures of Processor Systems (APS) lab work
|
||||
* Organization : National Research University of Electronic Technology (MIET)
|
||||
* Department : Institute of Microdevices and Control Systems
|
||||
* Author(s) : Andrei Solodovnikov
|
||||
* Email(s) : hepoh@org.miet.ru
|
||||
|
||||
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
|
||||
* ------------------------------------------------------------------------------
|
||||
*/
|
||||
module tb_top_asic();
|
||||
|
||||
logic clk100mhz_i;
|
||||
logic aresetn_i;
|
||||
logic rx_i;
|
||||
logic tx_o;
|
||||
logic clk_i;
|
||||
logic rst_i;
|
||||
|
||||
assign aresetn_i = !rst_i;
|
||||
|
||||
logic rx_busy, rx_valid, tx_busy, tx_valid;
|
||||
logic [7:0] rx_data, tx_data;
|
||||
|
||||
logic [3:0] [7:0] flash_addr;
|
||||
logic [3:0] [7:0] instr_size;
|
||||
logic [3:0] [7:0] instr_size_ack;
|
||||
logic [3:0] [7:0] data_size;
|
||||
logic [3:0] [7:0] data_size_ack;
|
||||
logic [3:0] [7:0] tiff_size;
|
||||
logic [3:0] [7:0] tiff_size_ack;
|
||||
|
||||
logic [7:0] instr_mem_byte[$];
|
||||
logic [7:0] data_mem_byte[$];
|
||||
logic [7:0] tiff_mem_byte [$];
|
||||
|
||||
localparam INIT_MSG_SIZE = 40;
|
||||
localparam MSG_DONE_SIZE = 57;
|
||||
localparam MSG_ACK_SIZE = 4;
|
||||
|
||||
byte init_str[INIT_MSG_SIZE];
|
||||
byte done_str[MSG_DONE_SIZE];
|
||||
|
||||
always #50ns clk_i = !clk_i;
|
||||
always #5ns clk100mhz_i = !clk100mhz_i;
|
||||
|
||||
initial begin
|
||||
$timeformat(-9, 2, " ns", 3);
|
||||
clk_i = 0;
|
||||
clk100mhz_i = 0;
|
||||
rst_i <= 0;
|
||||
@(posedge clk_i);
|
||||
rst_i <= 1;
|
||||
repeat(2) @(posedge clk_i);
|
||||
rst_i <= 0;
|
||||
instr_size = instr_mem_byte.size();
|
||||
data_size = data_mem_byte.size();
|
||||
tiff_size = tiff_mem_byte.size();
|
||||
|
||||
/*
|
||||
RCV_NEXT_COMMAND
|
||||
*/
|
||||
flash_addr = 32'h0000;
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = flash_addr[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
|
||||
/*
|
||||
INIT_MSG
|
||||
*/
|
||||
for(int i = 0; i < INIT_MSG_SIZE; i++) begin
|
||||
@(posedge clk_i);
|
||||
while(!rx_valid)@(posedge clk_i);
|
||||
init_str[i] = rx_data;
|
||||
end
|
||||
$display("%s", init_str);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
repeat(10000)@(posedge clk_i);
|
||||
|
||||
/*
|
||||
IDLE, RCV_INSTR_SIZE
|
||||
*/
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = instr_size[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
INSTR_SIZE_ACK
|
||||
*/
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
while(!rx_valid) @(posedge clk_i);
|
||||
instr_size_ack[i] = rx_data;
|
||||
@(posedge clk_i);
|
||||
end
|
||||
assert(instr_size_ack == instr_size)
|
||||
else $error("ack: %0h, size: %0h", instr_size_ack, instr_size);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
|
||||
/*
|
||||
INSTR_FLASH
|
||||
*/
|
||||
if(instr_size)repeat(10000)@(posedge clk_i);
|
||||
for(int i = instr_size-1; i >=0; i--) begin
|
||||
tx_data = instr_mem_byte[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
INSTR_FLASH_ACK
|
||||
*/
|
||||
for(int i = 0; i < MSG_DONE_SIZE; i++) begin
|
||||
@(posedge clk_i);
|
||||
while(!rx_valid)@(posedge clk_i);
|
||||
done_str[i] = rx_data;
|
||||
end
|
||||
$display("%t %s", $time, done_str);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
|
||||
repeat(10000)@(posedge clk_i);
|
||||
|
||||
|
||||
/*
|
||||
RCV_NEXT_COMMAND
|
||||
*/ flash_addr = 32'h4000;
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = flash_addr[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
|
||||
|
||||
/*
|
||||
INIT_MSG
|
||||
*/
|
||||
for(int i = 0; i < INIT_MSG_SIZE; i++) begin
|
||||
@(posedge clk_i);
|
||||
while(!rx_valid)@(posedge clk_i);
|
||||
init_str[i] = rx_data;
|
||||
end
|
||||
$display("%s", init_str);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
/*
|
||||
RCV_DATA_SIZE
|
||||
*/
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = data_size[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
DATA_SIZE_ACK
|
||||
*/
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
while(!rx_valid) @(posedge clk_i);
|
||||
data_size_ack[i] = rx_data;
|
||||
@(posedge clk_i);
|
||||
end
|
||||
assert(data_size_ack == data_size)
|
||||
else $error("ack: %0h, size: %0h", data_size_ack, data_size);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
DATA_FLASH
|
||||
*/
|
||||
if(data_size)repeat(10000)@(posedge clk_i);
|
||||
for(int i = data_size-1; i >=0; i--) begin
|
||||
tx_data = data_mem_byte[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
DATA_FLASH_ACK
|
||||
*/
|
||||
for(int i = 0; i < MSG_DONE_SIZE; i++) begin
|
||||
@(posedge clk_i);
|
||||
while(!rx_valid)@(posedge clk_i);
|
||||
done_str[i] = rx_data;
|
||||
end
|
||||
$display("%t %s", $time, done_str);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
repeat(10000)@(posedge clk_i);
|
||||
|
||||
|
||||
/*
|
||||
RCV_NEXT_COMMAND
|
||||
*/ flash_addr = 32'h0800_0000;
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = flash_addr[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
|
||||
/*
|
||||
INIT_MSG
|
||||
*/
|
||||
for(int i = 0; i < INIT_MSG_SIZE; i++) begin
|
||||
@(posedge clk_i);
|
||||
while(!rx_valid)@(posedge clk_i);
|
||||
init_str[i] = rx_data;
|
||||
end
|
||||
$display("%s", init_str);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
/*
|
||||
RCV_TIFF_SIZE
|
||||
*/
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = tiff_size[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
TIFF_SIZE_ACK
|
||||
*/
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
while(!rx_valid) @(posedge clk_i);
|
||||
tiff_size_ack[i] = rx_data;
|
||||
@(posedge clk_i);
|
||||
end
|
||||
assert(tiff_size_ack == tiff_size)
|
||||
else $display("ack: %0h, size: %0h", tiff_size_ack, tiff_size);
|
||||
wait(tx_o);
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
|
||||
/*
|
||||
TIFF_FLASH
|
||||
*/
|
||||
if(tiff_size)repeat(10000)@(posedge clk_i);
|
||||
for(int i = tiff_size-1; i >=0; i--) begin
|
||||
tx_data = tiff_mem_byte[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
// ----------------------------------------------
|
||||
|
||||
|
||||
/*
|
||||
TIFF_FLASH_ACK, FINISH
|
||||
*/
|
||||
for(int i = 0; i < MSG_DONE_SIZE; i++) begin
|
||||
@(posedge clk_i);
|
||||
while(!rx_valid)@(posedge clk_i);
|
||||
done_str[i] = rx_data;
|
||||
end
|
||||
$display("%t %s", $time, done_str);
|
||||
wait(!rx_busy)
|
||||
@(posedge clk_i)
|
||||
|
||||
/*
|
||||
RCV_NEXT_COMMAND
|
||||
*/ flash_addr = 32'hFFFF_FFFF;
|
||||
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
|
||||
tx_data = flash_addr[i];
|
||||
tx_valid = 1'b1;
|
||||
@(posedge clk_i);
|
||||
tx_valid = 1'b0;
|
||||
@(posedge clk_i);
|
||||
while(tx_busy) @(posedge clk_i);
|
||||
end
|
||||
assert(!DUT.core_reset) $display("Rooom to tooom");
|
||||
else $error("stall is not equal zero at the end");
|
||||
// ----------------------------------------------
|
||||
|
||||
repeat(10000)@(posedge clk_i);
|
||||
|
||||
$finish();
|
||||
end
|
||||
|
||||
|
||||
riscv_unit DUT(
|
||||
.clk_i (clk100mhz_i),
|
||||
.resetn_i (aresetn_i),
|
||||
.rx_i (rx_i),
|
||||
.tx_o (tx_o)
|
||||
);
|
||||
|
||||
uart_rx rx(
|
||||
.clk_i (clk_i ),
|
||||
.rst_i (rst_i ),
|
||||
.rx_i (tx_o ),
|
||||
.busy_o (rx_busy ),
|
||||
.baudrate_i (17'd115200 ),
|
||||
.parity_en_i(1'b1 ),
|
||||
.stopbit_i (1'b1 ),
|
||||
.rx_data_o (rx_data ),
|
||||
.rx_valid_o (rx_valid )
|
||||
);
|
||||
|
||||
uart_tx tx(
|
||||
.clk_i (clk_i ),
|
||||
.rst_i (rst_i ),
|
||||
.tx_o (rx_i ),
|
||||
.busy_o (tx_busy ),
|
||||
.baudrate_i (17'd115200 ),
|
||||
.parity_en_i(1'b1 ),
|
||||
.stopbit_i (1'b1 ),
|
||||
.tx_data_i (tx_data ),
|
||||
.tx_valid_i (tx_valid )
|
||||
);
|
||||
|
||||
initial instr_mem_byte = {
|
||||
8'h93, 8'h00, 8'h10, 8'h00, 8'h37, 8'h01, 8'h00, 8'h06, 8'hB7, 8'hC1, 8'h01, 8'h00, 8'h93, 8'h81, 8'h01, 8'h20,
|
||||
8'h23, 8'h26, 8'h31, 8'h00, 8'h13, 8'h02, 8'h10, 8'h00, 8'h23, 8'h28, 8'h41, 8'h00, 8'h93, 8'h02, 8'h10, 8'h00,
|
||||
8'h93, 8'h80, 8'h10, 8'h00, 8'h83, 8'h23, 8'h81, 8'h00, 8'h63, 8'h14, 8'h70, 8'h00, 8'h6F, 8'h00, 8'h00, 8'h00,
|
||||
8'h6F, 8'h00, 8'h00, 8'h00, 8'h23, 8'h20, 8'h11, 8'h00, 8'h6F, 8'h00, 8'h00, 8'h00
|
||||
};
|
||||
|
||||
initial #1 data_mem_byte = instr_mem_byte;
|
||||
|
||||
initial tiff_mem_byte = {
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000101, 8'b00000101, 8'b00000101, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00010010, 8'b00010010, 8'b00111111, 8'b00010010, 8'b00010010, 8'b00010010, 8'b00111111, 8'b00010010, 8'b00010010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000100, 8'b00001110, 8'b00010001, 8'b00010001, 8'b00000001, 8'b00001110, 8'b00010000, 8'b00010000, 8'b00010001, 8'b00010001, 8'b00001110, 8'b00000100, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000010, 8'b00000101, 8'b01000101, 8'b00100010, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00100010, 8'b01010001, 8'b01010000, 8'b00100000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00001100, 8'b00010010, 8'b00010010, 8'b00010010, 8'b01001100, 8'b01001010, 8'b00110001, 8'b00100001, 8'b00110001, 8'b01001110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000010, 8'b00000010, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000010, 8'b00000100, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000010, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00010010, 8'b00001100, 8'b00111111, 8'b00001100, 8'b00010010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000100, 8'b00000100, 8'b00011111, 8'b00000100, 8'b00000100, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000010, 8'b00000010, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00001111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00010000, 8'b00010000, 8'b00001000, 8'b00001000, 8'b00000100, 8'b00000100, 8'b00000010, 8'b00000010, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00110001, 8'b00101001, 8'b00101001, 8'b00100101, 8'b00100101, 8'b00100011, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00001000, 8'b00001100, 8'b00001010, 8'b00001001, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100000, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00000001, 8'b00111111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100000, 8'b00100000, 8'b00011100, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00010000, 8'b00011000, 8'b00010100, 8'b00010010, 8'b00010001, 8'b00111111, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00111111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00011111, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011100, 8'b00000010, 8'b00000001, 8'b00000001, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00111111, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111110, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000010, 8'b00000010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000010, 8'b00000010, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00000010, 8'b00000100, 8'b00001000, 8'b00010000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00111111, 8'b00000000, 8'b00111111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000001, 8'b00000010, 8'b00000100, 8'b00001000, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100000, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000000, 8'b00000100, 8'b00000100, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00111100, 8'b01000010, 8'b10011001, 8'b10100001, 8'b10111001, 8'b10100101, 8'b01111001, 8'b00000010, 8'b01111100, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00001111, 8'b00010001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00010001, 8'b00001111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00111111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00001111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00111111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00111111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00001111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00111001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100001, 8'b00100001, 8'b00010001, 8'b00001001, 8'b00000111, 8'b00001001, 8'b00010001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00111111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b01000001, 8'b01100011, 8'b01010101, 8'b01001001, 8'b01001001, 8'b01000001, 8'b01000001, 8'b01000001, 8'b01000001, 8'b01000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100001, 8'b00100011, 8'b00100101, 8'b00101001, 8'b00110001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00101001, 8'b00110001, 8'b00111110, 8'b00100000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011111, 8'b00010001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00000001, 8'b00000010, 8'b00001100, 8'b00010000, 8'b00100000, 8'b00100000, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b01111111, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b01000001, 8'b01000001, 8'b01000001, 8'b01000001, 8'b00100010, 8'b00100010, 8'b00010100, 8'b00010100, 8'b00001000, 8'b00001000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b01000001, 8'b01000001, 8'b01000001, 8'b01000001, 8'b01001001, 8'b01001001, 8'b01001001, 8'b01010101, 8'b01100011, 8'b01000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00010010, 8'b00001100, 8'b00001100, 8'b00010010, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b01000001, 8'b01000001, 8'b00100010, 8'b00100010, 8'b00010100, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00001000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00111111, 8'b00100000, 8'b00100000, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00000001, 8'b00111111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000111, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000010, 8'b00000010, 8'b00000100, 8'b00000100, 8'b00001000, 8'b00001000, 8'b00010000, 8'b00010000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000111, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000111, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000100, 8'b00001010, 8'b00010001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00111111, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00100000, 8'b00111110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00111110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00111111, 8'b00000001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011100, 8'b00100010, 8'b00000010, 8'b00000010, 8'b00001111, 8'b00000010, 8'b00000010, 8'b00000010, 8'b00000010, 8'b00000010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00110001, 8'b00101110, 8'b00100000, 8'b00100001, 8'b00011110, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000001, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00010000, 8'b00000000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010001, 8'b00010001, 8'b00001110, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00100001, 8'b00100001, 8'b00010001, 8'b00001111, 8'b00010001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00110111, 8'b01001001, 8'b01001001, 8'b01001001, 8'b01001001, 8'b01001001, 8'b01000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011111, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00011111, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00111110, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111110, 8'b00100000, 8'b00100000, 8'b00100000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011101, 8'b00000011, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00100001, 8'b00000001, 8'b00011110, 8'b00100000, 8'b00100001, 8'b00011110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000100, 8'b00000100, 8'b00011111, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00011000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00111110, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b01000001, 8'b01000001, 8'b00100010, 8'b00100010, 8'b00010100, 8'b00010100, 8'b00001000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b01000001, 8'b01000001, 8'b01001001, 8'b01001001, 8'b01001001, 8'b01010101, 8'b00100010, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b01000001, 8'b00100010, 8'b00010100, 8'b00001000, 8'b00010100, 8'b00100010, 8'b01000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00100001, 8'b00110001, 8'b00101110, 8'b00100000, 8'b00010000, 8'b00001111, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00111111, 8'b00010000, 8'b00001000, 8'b00000100, 8'b00000010, 8'b00000001, 8'b00111111, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00011000, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000011, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00011000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00000011, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00011000, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000100, 8'b00000011, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000000, 8'b00100110, 8'b00011001, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000,
|
||||
8'b00000000, 8'b00000011, 8'b00000101, 8'b00000101, 8'b00000011, 8'b00000000, 8'b00001100, 8'b00001100, 8'b00000100, 8'b00101100, 8'b00100000, 8'b00100000, 8'b01100000, 8'b00000000, 8'b00000000, 8'b00000000
|
||||
};
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user