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ЛР7. Переименование DUT в тб

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This commit is contained in:
Andrei Solodovnikov
2024-10-04 19:38:36 +03:00
committed by GitHub
parent 811c2f467d
commit 4875fb8ff8
1 changed files with 5 additions and 5 deletions
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10
Labs/07. Datapath/lab_07.tb_processor_system.sv
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@@ -13,7 +13,7 @@ module lab_07_tb_processor_system();
reg clk;
reg rst;
processor_system system(
processor_system DUT(
.clk_i(clk),
.rst_i(rst)
);
@@ -34,12 +34,12 @@ module lab_07_tb_processor_system();
end
stall_seq: assert property (
@(posedge system.core.clk_i) disable iff ( system.core.rst_i )
system.core.mem_req_o |-> (system.core.stall_i || $past(system.core.stall_i))
@(posedge DUT.core.clk_i) disable iff ( DUT.core.rst_i )
DUT.core.mem_req_o |-> (DUT.core.stall_i || $past(DUT.core.stall_i))
)else $error("\nincorrect implementation of stall signal\n");
stall_seq_fall: assert property (
@(posedge system.core.clk_i) disable iff ( system.core.rst_i )
(system.core.stall_i) |=> !system.core.stall_i
@(posedge DUT.core.clk_i) disable iff ( DUT.core.rst_i )
(DUT.core.stall_i) |=> !DUT.core.stall_i
)else $error("\nstall must fall exact one cycle after rising\n");
endmodule