From 4875fb8ff86ee33093dc6843fcbe32787631ce61 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Fri, 4 Oct 2024 19:38:36 +0300 Subject: [PATCH] =?UTF-8?q?=D0=9B=D0=A07.=20=D0=9F=D0=B5=D1=80=D0=B5=D0=B8?= =?UTF-8?q?=D0=BC=D0=B5=D0=BD=D0=BE=D0=B2=D0=B0=D0=BD=D0=B8=D0=B5=20DUT=20?= =?UTF-8?q?=D0=B2=20=D1=82=D0=B1?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/07. Datapath/lab_07.tb_processor_system.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Labs/07. Datapath/lab_07.tb_processor_system.sv b/Labs/07. Datapath/lab_07.tb_processor_system.sv index 0233ae6..49f5cbd 100644 --- a/Labs/07. Datapath/lab_07.tb_processor_system.sv +++ b/Labs/07. Datapath/lab_07.tb_processor_system.sv @@ -13,7 +13,7 @@ module lab_07_tb_processor_system(); reg clk; reg rst; - processor_system system( + processor_system DUT( .clk_i(clk), .rst_i(rst) ); @@ -34,12 +34,12 @@ module lab_07_tb_processor_system(); end stall_seq: assert property ( - @(posedge system.core.clk_i) disable iff ( system.core.rst_i ) - system.core.mem_req_o |-> (system.core.stall_i || $past(system.core.stall_i)) + @(posedge DUT.core.clk_i) disable iff ( DUT.core.rst_i ) + DUT.core.mem_req_o |-> (DUT.core.stall_i || $past(DUT.core.stall_i)) )else $error("\nincorrect implementation of stall signal\n"); stall_seq_fall: assert property ( - @(posedge system.core.clk_i) disable iff ( system.core.rst_i ) - (system.core.stall_i) |=> !system.core.stall_i + @(posedge DUT.core.clk_i) disable iff ( DUT.core.rst_i ) + (DUT.core.stall_i) |=> !DUT.core.stall_i )else $error("\nstall must fall exact one cycle after rising\n"); endmodule