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Merge branch 'master' of github.com:MPSU/APS

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This commit is contained in:
Andrei Solodovnikov
2024-09-12 09:20:06 +03:00
parent 4c7cbb82fa 773568589f
commit 4169b6645b
18 changed files with 335 additions and 350 deletions
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3
Labs/01. Adder/lab_01.tb_fulladder.sv
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@@ -38,6 +38,9 @@ module lab_01_tb_fulladder();
end
$display("\nTest has been finished. Check results at waveform window.\n");
$finish();
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end
endmodule

3
Labs/01. Adder/lab_01.tb_fulladder32.sv
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@@ -36,6 +36,9 @@ module lab_01_tb_fulladder32();
random_test();
$display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
$finish();
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end
task sequential_add_test();

3
Labs/01. Adder/lab_01.tb_fulladder4.sv
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@@ -38,6 +38,9 @@ module lab_01_tb_fulladder4();
end
$display("\nTest has been finished Check results at waveform window.\n");
$finish();
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end
endmodule

2
Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv
View File

@@ -45,7 +45,7 @@ module nexys_alu(
logic [31:0] result;
logic flag;
alu_riscv alu_riscv (
alu alu_riscv (
.alu_op_i (operator),
.a_i (operand_a),
.b_i (operand_b),

26
Labs/02. Arithmetic-logic unit/lab_02.tb_alu.sv
View File

@@ -63,6 +63,9 @@ initial
direct_test();
$display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
$finish();
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end
task X_test();
@@ -247,23 +250,22 @@ end
endmodule
parameter ALUOP_W = 5;
parameter OP_W = 32;
parameter SHIFT_W = $clog2(OP_W);
parameter STAGE_LEN = OP_W+1;
parameter HASH_LEN = 1000;
parameter START_CODING = 10366;
parameter START_MUX = START_CODING+100;
module alu_ref (
input logic [ALUOP_W-1:0] alu_op_i,
input logic [OP_W-1:0] a_i,
input logic [OP_W-1:0] b_i,
output logic [OP_W-1:0] result_o,
input logic [ 4:0] alu_op_i,
input logic [31:0] a_i,
input logic [31:0] b_i,
output logic [31:0] result_o,
output logic flag_o
);
localparam ALUOP_W = 5;
localparam OP_W = 32;
localparam SHIFT_W = $clog2(OP_W);
localparam STAGE_LEN = OP_W+1;
localparam HASH_LEN = 1000;
localparam START_CODING = 10366;
localparam START_MUX = START_CODING+100;
genvar i, j, k;

2
Labs/03. Register file and memory/board files/nexys_rf_riscv.sv
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@@ -34,7 +34,7 @@ module nexys_rf_riscv(
logic [7:0][3:0] rd1;
logic [7:0][3:0] rd2;
rf_riscv rf_riscv (
register_file rf_riscv (
.clk_i (clk_i),
.read_addr1_i (ra1 ),
.read_addr2_i (ra2 ),

33
Labs/03. Register file and memory/lab_03.tb_register_file.sv
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@@ -148,8 +148,39 @@ module lab_03_tb_register_file();
err_count = err_count + 1;
end
end
if( !err_count ) $display("\nregister file SUCCESS!!!\n");
//Incorrect read check
@(posedge CLK);
WA <= 5'd1;
WD <= 1;
WE <= 1'b1;
@(posedge CLK);
WA <= 5'd2;
WD <= 2;
WE <= 1'b1;
@(posedge CLK);
WE <= 1'b0;
RA1 <= 5'd1;
RA2 <= 5'd1;
@(posedge CLK);
WA <= 5'd31;
WE <= 1'b1;
WD <= 0;
RA1 <= 5'd2;
RA2 <= 5'd2;
@(posedge CLK);
if(RD1ref !== RD1) begin
$display("time = %0t, address %h, RD1. Invalid data %h, correct data %h", $time, RA1, RD1, RD1ref);
err_count = err_count + 1;
end
if(RD2ref !== RD2) begin
$display("time = %0t, address %h, RD2. Invalid data %h, correct data %h", $time, RA2, RD2, RD2ref);
err_count = err_count + 1;
end
$display("\nTest has been finished\nNumber of errors: %d\n", err_count);
$finish();
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.")
$fatal();
end
endmodule

3
Labs/04. Primitive programmable device/lab_04.tb_cybercobra.sv
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@@ -36,6 +36,9 @@ module lab_04_tb_CYBERcobra();
#10000;
$display("\n The test is over \n See the internal signals of the CYBERcobra on the waveform \n");
$finish;
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end
endmodule

13
Labs/05. Main decoder/lab_05.tb_decoder.sv
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@@ -15,7 +15,7 @@ module lab_05_tb_decoder();
typedef class riscv_instr;
riscv_instr instr = new();
logic clk, test_has_been_finished;
logic clk;
logic [31:0] fetched_instr_i = '0;
int err_count;
@@ -136,8 +136,10 @@ module lab_05_tb_decoder();
illegal_instrs_random_test();
$display("\nTest has been finished\nNumber of errors: %d\n", err_count);
test_has_been_finished = 1'b1;
$finish();
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end
function void randomize_with_given_opcode(input logic[4:0] given_opcode);
@@ -348,17 +350,12 @@ module lab_05_tb_decoder();
bit test_paused_by_errs;
initial begin
clk = '0;
test_has_been_finished = '0;
err_count = '0;
test_paused_by_errs = '0;
end
always #5 clk = ~clk;
always @(posedge clk) begin
if(test_has_been_finished) begin
$finish();
end
end
always @(posedge clk) begin
if((err_count >= 10) & !test_paused_by_errs) begin

13
Labs/06. Main memory/lab_06.tb_data_mem.sv
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@@ -30,8 +30,6 @@ module lab_06_tb_data_mem;
int err_cnt = 0;
static bit simulation_finished;
data_mem DUT (.*);
task read_request(input logic [31:0] address, output logic [31:0] data);
@@ -173,8 +171,10 @@ module lab_06_tb_data_mem;
random_test();
$display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
simulation_finished = 1;
$finish;
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end
logic [31:0] ram_data;
@@ -275,13 +275,6 @@ module lab_06_tb_data_mem;
$display("Error at %t. ram[%d][31:24] is unstable without write request", $time(), $sampled(addr_reg));
end
always @(posedge clk_i) begin
if(simulation_finished) begin
$finish;
end
end
always @(posedge clk_i) begin
if (err_cnt >= 10) begin
$display("\nTest has been stopped after 10 errors"); $stop();

2
Labs/07. Datapath/board files/nexys_riscv_unit.sv
View File

@@ -98,7 +98,7 @@ module nexys_riscv_unit(
.O (bufg_clk )
);
riscv_unit unit(
processor_system unit(
.clk_i (bufg_clk),
.rst_i (!arstn_i)
);

3
Labs/07. Datapath/lab_07.tb_processor_system.sv
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@@ -28,6 +28,9 @@ module lab_07_tb_processor_system();
#800;
$display("\n The test is over \n See the internal signals of the module on the waveform \n");
$finish;
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end
stall_seq: assert property (

3
Labs/08. Load-store unit/lab_08.tb_lsu.sv
View File

@@ -63,6 +63,9 @@ initial begin
repeat(3e3)@(posedge clk_i);
$display("Simulation finished. Number of errors: %d", err_count);
$finish();
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end
initial begin

28
Labs/Made-up modules/lab_02.alu.sv
View File

@@ -1,6 +1,6 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* File : alu_riscv.sv
* File : alu.sv
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Alexey Kozin
@@ -10,22 +10,22 @@ See LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
parameter ALUOP_W = 5;
parameter OP_W = 32;
parameter SHIFT_W = $clog2(OP_W);
parameter STAGE_LEN = OP_W+1;
parameter HASH_LEN = 1000;
parameter START_CODING = 10366;
parameter START_MUX = START_CODING+100;
module alu_riscv (
input logic [ALUOP_W-1:0] alu_op_i,
input logic [OP_W-1:0] a_i,
input logic [OP_W-1:0] b_i,
output logic [OP_W-1:0] result_o,
module alu (
input logic [4:0] alu_op_i,
input logic [31:0] a_i,
input logic [31:0] b_i,
output logic [31:0] result_o,
output logic flag_o
);
localparam ALUOP_W = 5;
localparam OP_W = 32;
localparam SHIFT_W = $clog2(OP_W);
localparam STAGE_LEN = OP_W+1;
localparam HASH_LEN = 1000;
localparam START_CODING = 10366;
localparam START_MUX = START_CODING+100;
genvar i, j, k;
logic [OP_W-1:0] skjfbsbgisg [0:STAGE_LEN-1];

54
Labs/Made-up modules/lab_03.data_mem.sv
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@@ -1,54 +0,0 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module data_mem (
input logic clk_i,
input logic [31:0] addr_i,
input logic [31:0] write_data_i,
input logic write_enable_i,
input logic mem_req_i,
output logic [31:0] read_data_o
);
`define akjsdnnaskjdndat $clog2(128)
`define cdyfguvhbjnmkdat $clog2(`akjsdnnaskjdndat)
`define qwenklfsaklasddat $clog2(`cdyfguvhbjnmkdat)
`define asdasdhkjasdsadat (34>>`cdyfguvhbjnmkdat)
logic [31:0] RAM [0:4095];
logic [31:0] addr;
assign addr = {20'b0, addr_i[13:2]};
always_ff @(posedge clk_i) begin
if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][{5{1'b1}}:{3'd7,2'b00}] <= write_data_i['h1f:'h1c];
if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][19:{1'b1,4'h0}] <= write_data_i[42-23-:`asdasdhkjasdsadat];
if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][{3{1'b1}}:{1'b1,2'h0}] <= write_data_i[`akjsdnnaskjdndat-:`asdasdhkjasdsadat];
if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][23:{{2{2'b10}},1'b0}] <= write_data_i[42-19-:`asdasdhkjasdsadat];
if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][27:{2'b11,3'b000}] <= write_data_i['h1b:'h18];
if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][11:{1'b1,{3{1'b0}}}] <= write_data_i[`akjsdnnaskjdndat+`asdasdhkjasdsadat:(`akjsdnnaskjdndat+`asdasdhkjasdsadat)-`cdyfguvhbjnmkdat];
if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][{2{1'b1}}:{3{1'b0}}] <= write_data_i[`akjsdnnaskjdndat-`asdasdhkjasdsadat-:`asdasdhkjasdsadat];
if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][{4{1'b1}}:4'b1100] <= write_data_i[(`akjsdnnaskjdndat<<(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat)) + (`asdasdhkjasdsadat-`cdyfguvhbjnmkdat):12];
end
always_ff@(posedge clk_i) begin
case(1)
mem_req_i&&!write_enable_i: begin
read_data_o['h1f:'h1c]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][{5{1'b1}}:{3'd7,2'b00}];
read_data_o[42-23-:`asdasdhkjasdsadat]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][19:{1'b1,4'h0}];
read_data_o[`akjsdnnaskjdndat-:`asdasdhkjasdsadat]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][{3{1'b1}}:{1'b1,2'h0}];
read_data_o[42-19-:`asdasdhkjasdsadat]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][23:{{2{2'b10}},1'b0}];
read_data_o['h1b:'h18]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][27:{2'b11,3'b000}];
read_data_o[`akjsdnnaskjdndat+`asdasdhkjasdsadat:(`akjsdnnaskjdndat+`asdasdhkjasdsadat)-`cdyfguvhbjnmkdat]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][11:8];
read_data_o[`akjsdnnaskjdndat-`asdasdhkjasdsadat-:`asdasdhkjasdsadat]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][3:0];
read_data_o[(`akjsdnnaskjdndat<<(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat))+(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat):12]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][{4{1'b1}}:12];
end
default: read_data_o <= read_data_o;
endcase
end
endmodule

4
Labs/Made-up modules/lab_03.instr_mem.sv
View File

@@ -2,8 +2,8 @@
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------

2
Labs/Made-up modules/lab_03.register_file.sv
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@@ -8,7 +8,7 @@
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module rf_riscv(
module register_file(
input logic clk_i,
input logic write_enable_i,

4
Labs/README.md
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@@ -133,9 +133,7 @@ https://github.com/MPSU/APS/assets/17159587/4daac01f-dc9a-4ec8-8d3f-c5dc1ef97119
## 6. Основная память
Недостатком реализации процессора из предыдущей лабораторной работы была его неспособность выполнять операции `LB`, `LBU`, `SB`, `LH`, `LHU`, `SH`. Отчасти это связано с ограничением реализованной ранее памяти (в этой памяти не было возможности обновить отдельный байт в ячейке памяти).
Данная вспомогательная лабораторная работа позволяет реализовать память без этого ограничения.
Процессор CYBERcobra 2000 использовал в качестве основного хранилища данных регистровый файл, однако на практике 31-го регистра недостаточно для выполнения сложных программ. Для этих целей используется **основная память**.
## 7. Тракт данных