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45 lines
1.2 KiB
Systemverilog
45 lines
1.2 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Nikita Bulavin
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* Email(s) : nekkit6@edu.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module lab_04_tb_CYBERcobra();
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CYBERcobra dut(
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.clk_i(clk),
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.rst_i(rstn),
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.sw_i (sw_i ),
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.out_o(OUT)
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);
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wire [31:0] OUT;
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reg clk;
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reg rstn;
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reg [15:0] sw_i;
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initial clk <= 0;
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always #5 clk = ~clk;
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initial begin
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$display("Test has been started");
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rstn = 1'b1;
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#10;
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rstn = 1'b0;
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sw_i = 16'b100001000; //значение, до которого считает счетчик
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//#260;
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//sw_i = 15'b0;
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#10000;
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$display("\n The test is over \n See the internal signals of the CYBERcobra on the waveform \n");
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$finish;
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#5;
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$display("You're trying to run simulation that has finished. Aborting simulation.");
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$fatal();
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end
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endmodule
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