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ЛР5. Доработка тб
Правка выравниваний при выводе, причесывание циклов.
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@@ -203,7 +203,7 @@ module tb_decoder_riscv();
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So for every opcode we try 3 different instructions.
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*/
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foreach(opcode_array[i]) begin
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for(logic[1:0] j = 2'b00; j < 2'b11; j++) begin
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for(int j = 0; j < 3; j++) begin
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randomize_with_given_opcode(opcode_array[i]);
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@(posedge clk);
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fetched_instr_i <= {instr.bits[31:2], j};
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@@ -218,7 +218,7 @@ module tb_decoder_riscv();
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*/
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foreach(opcode_array[i]) begin
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automatic logic [4:0] incorrect_opcode;
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for(logic[1:0] j = 2'b00; j < 2'b11; j++) begin
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for(int j = 0; j < 3; j++) begin
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randomize_with_given_opcode(opcode_array[i]);
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@(posedge clk);
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assert(std::randomize(incorrect_opcode) with {!(incorrect_opcode inside {
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@@ -261,14 +261,14 @@ module tb_decoder_riscv();
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*/
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// Broken fence instructions
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for(logic [3:0] i = 3'd1; i <= 4'd7; i++) begin
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for(int i = 1; i < 8; i++) begin
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randomize_with_given_opcode(MISC_MEM_OPCODE);
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@(posedge clk);
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fetched_instr_i <= {instr.bits[31:15], i, instr.bits[11:0]};
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end
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// Broken ecall, ebreak, mret instructions
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for(logic [2:0] j = 3'd0; j <= 3'd3; j++) begin
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for(int j = 0; j < 3; j++) begin
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@(posedge clk);
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// broken imm field
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fetched_instr_i <= {12'd2, instr.system_instrs[j][19:0]};
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@@ -558,7 +558,7 @@ module tb_decoder_riscv();
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wb_sel_check |-> (grm_wb_sel_o === wb_sel_o )
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)
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else begin
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$display("wb_sel_o value is incorrect ( %b instead of %b), instruction: %s %s", wb_sel_o , grm_wb_sel_o, raw_instr, instr_str );
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$display("wb_sel_o value is incorrect ( %b instead of %b), instruction: %s %s", wb_sel_o , grm_wb_sel_o, raw_instr, instr_str );
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err_count++;
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end
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