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Ref(labs/03/board/top):Уд-ие лишнего условия в we

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alexkharl
2024-02-22 16:36:59 +03:00
parent e4eab315cc
commit 0a60eb436c
1 changed files with 1 additions and 1 deletions
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Labs/03. Register file and memory/board files/nexys_rf_riscv.sv
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@@ -147,7 +147,7 @@ module nexys_rf_riscv(
logic we_ff; logic we_ff;
logic we_next; logic we_next;
assign we_next = wd_en ? 1'b1 : 1'b0; assign we_next = wd_en;
always_ff @(posedge clk_i or negedge arstn_i) begin always_ff @(posedge clk_i or negedge arstn_i) begin
if (!arstn_i) we_ff <= 1'b0; if (!arstn_i) we_ff <= 1'b0;
else we_ff <= we_next; else we_ff <= we_next;