From 0a60eb436c20c287350883d3ebbec9642adc4f5e Mon Sep 17 00:00:00 2001 From: alexkharl Date: Thu, 22 Feb 2024 16:36:59 +0300 Subject: [PATCH] =?UTF-8?q?Ref(labs/03/board/top):=D0=A3=D0=B4-=D0=B8?= =?UTF-8?q?=D0=B5=20=D0=BB=D0=B8=D1=88=D0=BD=D0=B5=D0=B3=D0=BE=20=D1=83?= =?UTF-8?q?=D1=81=D0=BB=D0=BE=D0=B2=D0=B8=D1=8F=20=D0=B2=20we?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/03. Register file and memory/board files/nexys_rf_riscv.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv b/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv index 2bfdf05..0b839ce 100644 --- a/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv +++ b/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv @@ -147,7 +147,7 @@ module nexys_rf_riscv( logic we_ff; logic we_next; - assign we_next = wd_en ? 1'b1 : 1'b0; + assign we_next = wd_en; always_ff @(posedge clk_i or negedge arstn_i) begin if (!arstn_i) we_ff <= 1'b0; else we_ff <= we_next;