Ref(labs/03/board/top):Уд-ие лишнего условия в we

Labs/03. Register file and memory/board files/nexys_rf_riscv.sv

@@ -147,7 +147,7 @@ module nexys_rf_riscv(
 
   logic  we_ff;
   logic  we_next;
-  assign we_next = wd_en ? 1'b1 : 1'b0;
+  assign we_next = wd_en;
   always_ff @(posedge clk_i or negedge arstn_i) begin
     if (!arstn_i) we_ff <= 1'b0;
     else          we_ff <= we_next;