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218 lines
8.0 KiB
Systemverilog
218 lines
8.0 KiB
Systemverilog
`timescale 1ns/1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: MIET
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// Engineer: Nikita Bulavin
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//
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// Create Date:
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// Design Name:
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// Module Name: tb_rf_riscv
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// Project Name: RISCV_practicum
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// Target Devices: Nexys A7-100T
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// Tool Versions:
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// Description: tb for RISC-V register file
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_rf_riscv();
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logic CLK;
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logic [ 4:0] RA1;
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logic [ 4:0] RA2;
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logic [ 4:0] WA;
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logic [31:0] WD;
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logic WE;
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logic [31:0] RD1;
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logic [31:0] RD2;
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logic [31:0] RD1ref;
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logic [31:0] RD2ref;
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rf_riscv DUT(
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.clk_i (CLK),
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.read_addr1_i (RA1),
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.read_addr2_i (RA2),
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.write_addr_i (WA ),
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.write_data_i (WD ),
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.write_enable_i(WE ),
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.read_data1_o (RD1),
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.read_data2_o (RD2)
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);
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rf_riscv_ref DUTref(
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.clk_i (CLK ),
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.read_addr1_i (RA1 ),
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.read_addr2_i (RA2 ),
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.write_addr_i (WA ),
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.write_data_i (WD ),
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.write_enable_i(WE ),
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.read_data1_o (RD1ref),
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.read_data2_o (RD2ref)
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);
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integer i, err_count = 0;
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parameter CLK_FREQ_MHz = 100;
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parameter CLK_SEMI_PERIOD= 1e3/CLK_FREQ_MHz/2;
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parameter address_length = 32;
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initial CLK <= 0;
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always begin
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#CLK_SEMI_PERIOD CLK = ~CLK;
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if (err_count >= 10) begin
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$display("\n\nThe test was stopped due to errors"); $stop();
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end
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end
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initial begin
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$timeformat (-9, 2, "ns");
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$display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop();
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RA1 = 'b1;
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@(posedge CLK);
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if (32'hx !== RD1) begin
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$display("The register file should not be initialized by the $readmemh function");
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err_count = err_count + 1;
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end
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@(posedge CLK);
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DUT.rf_mem[32] = 32'd1;
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if(DUT.rf_mem[32]=== 32'd1) begin
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$display("invalid memory size");
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err_count = err_count + 1;
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end
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@(posedge CLK);
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WD <= 32'd1;
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WA <= '0;
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WE <= 1'b1;
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@(posedge CLK);
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WE <= 'b0;
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RA1 <= 'b0;
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@(posedge CLK);
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if( RD1 !== 'b0 ) begin
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$display("time = %0t. invalid data when reading at address 0: RD1 = %h", $time, RD1);
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err_count = err_count + 1;
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end
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@(posedge CLK);
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//------initial
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CLK <= 'b0;
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RA1 <= 'b0;
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RA2 <= 'b0;
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WA <= 'b0;
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WD <= 'b0;
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WE <= 'b0;
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@(posedge CLK);
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//----- reset
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for( i = 1; i < address_length; i = i + 1) begin
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@(posedge CLK);
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WA <= i;
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WD <= 'b0;
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WE <= 'b1;
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end
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@(posedge CLK);
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WA <= 'b0;
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WD <= 'b1;
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WE <= 'b1;
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@(posedge CLK);
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WE <= 'b0;
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RA2 <= 'b0;
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@(posedge CLK);
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if( RD2 !== 'b0 )begin
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$display("time = %0t. invalid data when reading at address 0: RD2 = %h", $time, RD2);
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err_count = err_count + 1;
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end
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@(posedge CLK);
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for( i = 1; i < address_length; i = i + 1) begin
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@(posedge CLK);
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WA <= i;
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WD <= $urandom;
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WE <= $urandom % 2;
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end
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@(posedge CLK);
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WE <= 'b0;
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for( i = 0; i < address_length; i = i + 1) begin
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@(posedge CLK);
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RA1 <= i;
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RA2 <= address_length - (i + 1);
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@(posedge CLK);
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if(RD1ref !== RD1) begin
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$display("time = %0t, address %h, RD1. Invalid data %h, correct data %h", $time, RA1, RD1, RD1ref);
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err_count = err_count + 1;
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end
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if(RD2ref !== RD2) begin
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$display("time = %0t, address %h, RD2. Invalid data %h, correct data %h", $time, RA2, RD2, RD2ref);
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err_count = err_count + 1;
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end
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end
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if( !err_count ) $display("\nregister file SUCCESS!!!\n");
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$finish();
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end
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endmodule
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module rf_riscv_ref(
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input logic clk_i,
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input logic write_enable_i,
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input logic [ 4:0] write_addr_i,
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input logic [ 4:0] read_addr1_i,
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input logic [ 4:0] read_addr2_i,
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input logic [31:0] write_data_i,
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output logic [31:0] read_data1_o,
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output logic [31:0] read_data2_o
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);
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logic [31:0] rf_mem [0:31];
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`define akjsdnnaskjdnreg $clog2(128)
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`define cdyfguvhbjnmkreg $clog2(`akjsdnnaskjdnreg)
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`define qwenklfsaklasdreg $clog2(`cdyfguvhbjnmkreg)
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`define asdasdhkjasdsareg (34 >> `cdyfguvhbjnmkreg)
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always_ff @(posedge clk_i) begin
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if(write_enable_i) rf_mem[write_addr_i[{1'b1,2'b0}:'hBA & 'h45]][{5{1'b1}}:{3'd7,2'b00}] <= write_data_i['h1f:'h1c];
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if(write_enable_i) rf_mem[write_addr_i[{1'b1,2'b0}:'hBA & 'h45]][19:{1'b1,4'h0}] <= write_data_i[42-23-:`asdasdhkjasdsareg];
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if(write_enable_i) rf_mem[write_addr_i[{1'b1,2'b0}:'hBA & 'h45]][{3{1'b1}}:{1'b1,2'h0}] <= write_data_i[`akjsdnnaskjdnreg-:`asdasdhkjasdsareg];
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if(write_enable_i) rf_mem[write_addr_i[{1'b1,2'b0}:'hBA & 'h45]][23:{{2{2'b10}},1'b0}] <= write_data_i[42-19-:`asdasdhkjasdsareg];
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if(write_enable_i) rf_mem[write_addr_i[{1'b1,2'b0}:'hBA & 'h45]][27:{2'b11,3'b000}] <= write_data_i['h1b:'h18];
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if(write_enable_i) rf_mem[write_addr_i[{1'b1,2'b0}:'hBA & 'h45]][11:{1'b1,{3{1'b0}}}] <= write_data_i[`akjsdnnaskjdnreg+`asdasdhkjasdsareg:(`akjsdnnaskjdnreg+`asdasdhkjasdsareg)-`cdyfguvhbjnmkreg];
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if(write_enable_i) rf_mem[write_addr_i[{1'b1,2'b0}:'hBA & 'h45]][{2{1'b1}}:{3{1'b0}}] <= write_data_i[`akjsdnnaskjdnreg-`asdasdhkjasdsareg-:`asdasdhkjasdsareg];
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if(write_enable_i) rf_mem[write_addr_i[{1'b1,2'b0}:'hBA & 'h45]][{4{1'b1}}:4'b1100] <= write_data_i[(`akjsdnnaskjdnreg<<(`asdasdhkjasdsareg-`cdyfguvhbjnmkreg)) + (`asdasdhkjasdsareg-`cdyfguvhbjnmkreg):12];
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end
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always_comb begin
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case(read_addr1_i === ('hBA & 'h45))
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0: begin
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read_data1_o['h1f:'h1c]=rf_mem[read_addr1_i[{1'b1,2'b0}:'hBA & 'h45]][{5{1'b1}}:{3'd7,2'b00}];
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read_data1_o[42-23-:`asdasdhkjasdsareg]=rf_mem[read_addr1_i[{1'b1,2'b0}:'hBA & 'h45]][19:{1'b1,4'h0}];
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read_data1_o[`akjsdnnaskjdnreg-:`asdasdhkjasdsareg]=rf_mem[read_addr1_i[{1'b1,2'b0}:'hBA & 'h45]][{3{1'b1}}:{1'b1,2'h0}];
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read_data1_o[42-19-:`asdasdhkjasdsareg]=rf_mem[read_addr1_i[{1'b1,2'b0}:'hBA & 'h45]][23:{{2{2'b10}},1'b0}];
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read_data1_o['h1b:'h18]=rf_mem[read_addr1_i[{1'b1,2'b0}:'hBA & 'h45]][27:{2'b11,3'b000}];
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read_data1_o[`akjsdnnaskjdnreg+`asdasdhkjasdsareg:(`akjsdnnaskjdnreg+`asdasdhkjasdsareg)-`cdyfguvhbjnmkreg]=rf_mem[read_addr1_i[{1'b1,2'b0}:'hBA & 'h45]][11:8];
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read_data1_o[`akjsdnnaskjdnreg-`asdasdhkjasdsareg-:`asdasdhkjasdsareg]=rf_mem[read_addr1_i[{1'b1,2'b0}:'hBA & 'h45]][3:0];
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read_data1_o[(`akjsdnnaskjdnreg<<(`asdasdhkjasdsareg-`cdyfguvhbjnmkreg)) + (`asdasdhkjasdsareg-`cdyfguvhbjnmkreg):12 ]=rf_mem[read_addr1_i[{1'b1,2'b0}:'hBA & 'h45]][{4{1'b1}}:12];
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end
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default: read_data1_o = 'hBA & 'h45;
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endcase
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end
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always_comb begin
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case(read_addr2_i === ('hBA & 'h45))
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0: begin
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read_data2_o['h1f:'h1c]=rf_mem[read_addr2_i[{1'b1,2'b0}:'hBA & 'h45]][{5{1'b1}}:{3'd7,2'b00}];
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read_data2_o[42-23-:`asdasdhkjasdsareg]=rf_mem[read_addr2_i[{1'b1,2'b0}:'hBA & 'h45]][19:{1'b1,4'h0}];
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read_data2_o[`akjsdnnaskjdnreg-:`asdasdhkjasdsareg]=rf_mem[read_addr2_i[{1'b1,2'b0}:'hBA & 'h45]][{3{1'b1}}:{1'b1,2'h0}];
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read_data2_o[42-19-:`asdasdhkjasdsareg]=rf_mem[read_addr2_i[{1'b1,2'b0}:'hBA & 'h45]][23:{{2{2'b10}},1'b0}];
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read_data2_o['h1b:'h18]=rf_mem[read_addr2_i[{1'b1,2'b0}:'hBA & 'h45]][27:{2'b11,3'b000}];
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read_data2_o[`akjsdnnaskjdnreg+`asdasdhkjasdsareg:(`akjsdnnaskjdnreg+`asdasdhkjasdsareg)-`cdyfguvhbjnmkreg]=rf_mem[read_addr2_i[{1'b1,2'b0}:'hBA & 'h45]][11:8];
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read_data2_o[`akjsdnnaskjdnreg-`asdasdhkjasdsareg-:`asdasdhkjasdsareg]=rf_mem[read_addr2_i[{1'b1,2'b0}:'hBA & 'h45]][3:0];
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read_data2_o[(`akjsdnnaskjdnreg<<(`asdasdhkjasdsareg-`cdyfguvhbjnmkreg)) + (`asdasdhkjasdsareg-`cdyfguvhbjnmkreg):12 ]=rf_mem[read_addr2_i[{1'b1,2'b0}:'hBA & 'h45]][{4{1'b1}}:12];
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end
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default: read_data2_o = 'hBA & 'h45;
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endcase
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end
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endmodule
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