APS/Labs/04. Primitive programmable device/board files

Testing CYBERcobra on FPGA

After verifying the design in simulation, you need to test it on an FPGA prototype.

Instructions for implementing the prototype are described here.

Fig. 1 shows the prototype schematic on the FPGA.

Figure 1. Block diagram of the nexys_CYBERcobra module.

The prototype allows you to execute the program stored in the instruction memory one clock cycle at a time. It also displays the operation currently being executed by the processor.

Note

The instance of the instr_mem module inside CYBERcobra must be named imem. That is, the instantiation line must look like this: instr_mem imem(...).

Peripheral Description

• Switches

  The values of switches SW[15:0] are passed directly to the sw_i port of the design module.

• Buttons

  • BTND — pressing this button generates a clock pulse delivered to the clk_i port of the design module.
  • CPU_RESET — connected to the rst_i input of the design module. Since CYBERcobra uses synchronous reset (i.e., the reset signal is only recognized on a rising clock edge), resetting the CYBERcobra module and its sub-modules requires holding down the reset button and then pressing the clock button.

• LEDs

  LEDs LED[15:0] display the lower 16 bits of the value currently present on the out_o port of the design module.

• Seven-Segment Displays

  The seven-segment displays are divided into 3 blocks (see Fig. 1):

  • out — displays the lower 8 bits of the value on the out_o port of the design module as a hexadecimal number.
  • PC — displays the lower 8 bits of the program counter, which is driven to the addr_i input of the instruction memory module, as a hexadecimal number.
  • operation — displays the operation currently being executed by the processor.

Operations Displayed by the Prototype

Mapping of instruction types to displayed operations:

1. Computational instructions — corresponds to the opcodes of ALU computational operations.
2. Load-immediate instruction — LI (from load immediate).
3. Load-from-external-device instruction — IN (from input).
4. Unconditional jump — JUMP.
5. Conditional branch instructions — corresponds to the opcodes of ALU comparison operations.

During the execution of computational instructions and conditional branch instructions, illegal operations may be encountered (displayed as ILL, from illegal). An operation is considered illegal in the following cases:

• If the ALU operation field of the instruction contains a bit pattern that is not within the range of valid values.
• If the instruction is a computational instruction but the ALU operation field contains a bit pattern corresponding to a flag-computing operation, or vice versa.

The instruction 0 0 11 xxxxxxxxxxxxxxxxxxxxxxxxxxxx is displayed as NOP (from no operation).

The mapping of operations to their representation on the seven-segment displays is shown in Fig. 2:

Figure 2. Mapping of operations to their representation on the seven-segment displays.

Demo Program

The recommended demo program is program.mem. A description of how it works can be found in the #final-overview section.