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55 lines
1.1 KiB
Verilog
55 lines
1.1 KiB
Verilog
module sys_clk_rst_gen#(
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parameter DIV_WIDTH = 4
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)(
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input ex_clk_i,
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input ex_areset_n_i,
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input [DIV_WIDTH-1:0] div_i,
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output sys_clk_o,
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output sys_reset_o
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);
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reg [1:0] ex_arstn_buf;
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reg [1:0] sys_rstn_buf;
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wire ex_arstn_buffered;
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assign ex_arstn_buffered = ex_arstn_buf[1];
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assign sys_reset_o = !sys_rstn_buf[1];
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always @(posedge ex_clk_i or negedge ex_areset_n_i) begin
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if(!ex_areset_n_i) begin
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ex_arstn_buf <= 2'b0;
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end
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else begin
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ex_arstn_buf <= {ex_arstn_buf[0], 1'b1};
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end
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end
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reg [DIV_WIDTH-1:0] cnt;
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reg clk_div;
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always@( posedge ex_clk_i or negedge ex_arstn_buffered ) begin
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if ( ~ex_arstn_buffered ) begin
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cnt <= 0;
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clk_div <= 0;
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end else if ( cnt == 0 ) begin
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cnt <= div_i;
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clk_div <= !clk_div;
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end else begin
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cnt <= cnt - 1;
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end
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end
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BUFG clkbuf (.O(sys_clk_o),.I(clk_div));
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always @(posedge sys_clk_o or negedge ex_arstn_buffered) begin
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if(!ex_arstn_buffered) begin
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sys_rstn_buf <= 2'b0;
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end
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else begin
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sys_rstn_buf <= {sys_rstn_buf[0], 1'b1};
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end
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end
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endmodule
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