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112 lines
3.3 KiB
Systemverilog
112 lines
3.3 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module lab_15_tb_bluster();
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logic clk_i;
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logic rst_i;
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logic rx_i;
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logic tx_o;
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logic [ 31:0] instr_addr_o;
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logic [ 31:0] instr_wdata_o;
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logic instr_we_o;
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logic [ 31:0] data_addr_o;
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logic [ 31:0] data_wdata_o;
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logic data_we_o;
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logic core_reset_o;
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logic rx_busy, rx_valid, tx_busy, tx_valid;
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logic [7:0] rx_data, tx_data;
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logic [31:0] instr_addr_i;
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logic [31:0] instr_rdata_o;
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import bluster_pkg::*;
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byte init_str[INIT_MSG_SIZE];
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byte done_str[FLASH_MSG_SIZE];
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always #50ns clk_i = !clk_i;
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initial begin
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$timeformat(-9, 2, " ns", 3);
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clk_i = 0;
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rst_i <= 0;
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@(posedge clk_i);
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rst_i <= 1;
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repeat(2) @(posedge clk_i);
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rst_i <= 0;
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program_region("lab_15_instr.mem", clk_i, tx_valid, rx_valid, tx_o, tx_busy, core_reset_o, rx_data, tx_data);
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program_region("lab_15_data.mem", clk_i, tx_valid, rx_valid, tx_o, tx_busy, core_reset_o, rx_data, tx_data);
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program_region("lab_15_char.mem", clk_i, tx_valid, rx_valid, tx_o, tx_busy, core_reset_o, rx_data, tx_data);
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finish_programming(clk_i, tx_valid, tx_busy, core_reset_o, tx_data);
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$finish();
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end
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bluster DUT(.*);
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uart_rx rx(
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.clk_i (clk_i ),
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.rst_i (rst_i ),
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.rx_i (tx_o ),
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.busy_o (rx_busy ),
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.baudrate_i (17'd115200 ),
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.parity_en_i(1'b1 ),
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.stopbit_i (2'b1 ),
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.rx_data_o (rx_data ),
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.rx_valid_o (rx_valid )
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);
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uart_tx tx(
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.clk_i (clk_i ),
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.rst_i (rst_i ),
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.tx_o (rx_i ),
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.busy_o (tx_busy ),
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.baudrate_i (17'd115200 ),
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.parity_en_i(1'b1 ),
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.stopbit_i (2'b1 ),
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.tx_data_i (tx_data ),
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.tx_valid_i (tx_valid )
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);
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rw_instr_mem imem(
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.clk_i (clk_i ) ,
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.read_addr_i (instr_addr_i ) ,
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.read_data_o (instr_rdata_o ) ,
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.write_addr_i (instr_addr_o ) ,
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.write_data_i (instr_wdata_o ) ,
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.write_enable_i(instr_we_o )
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);
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data_mem dmem(
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.clk_i (clk_i ),
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.mem_req_i (data_addr_o[31:24] == 0),
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.write_enable_i (data_we_o ),
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.byte_enable_i (4'b1111 ),
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.addr_i (data_addr_o ),
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.write_data_i (data_wdata_o ),
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.read_data_o (),
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.ready_o ()
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);
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data_mem cmem(
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.clk_i (clk_i ),
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.mem_req_i (data_addr_o[31:24] == 7),
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.write_enable_i (data_we_o ),
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.byte_enable_i (4'b1111 ),
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.addr_i (data_addr_o ),
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.write_data_i (data_wdata_o ),
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.read_data_o (),
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.ready_o ()
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);
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endmodule
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