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26 lines
345 B
Systemverilog
26 lines
345 B
Systemverilog
module vector_abs(
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input logic [31:0] x,
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input logic [31:0] y,
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output logic [31:0] abs
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);
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logic [31:0] min;
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logic [31:0] min_half;
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max_min max_min_unit(
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.a(x),
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.b(y),
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.max(max),
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.min(min)
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);
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half_divider div_unit(
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.numerator(min),
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.quotient(min_half)
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);
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assign abs = max + min_half;
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endmodule
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