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124 lines
2.4 KiB
Systemverilog
124 lines
2.4 KiB
Systemverilog
//////////////////////////////////////////////////////////////////////////////////
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// Company: Digilent Inc.
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// Engineer: Thomas Kappenman
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//
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// Create Date: 03/03/2015 09:33:36 PM
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// Design Name:
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// Module Name: PS2Receiver
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// Project Name: Nexys4DDR Keyboard Demo
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// Target Devices: Nexys4DDR
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// Tool Versions:
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// Description: PS2 Receiver module used to shift in keycodes from a keyboard plugged into the PS2 port
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// Modified in 2023 by engineers of
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// National Research University of Electronic Technology
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// Nikita Bulavin and Andrei Solodovnikov
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//
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//////////////////////////////////////////////////////////////////////////////////
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module PS2Receiver(
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input logic clk_i,
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input logic rst_i,
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input logic kclk_i,
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input logic kdata_i,
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output logic [7:0] keycode_o,
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output keycode_valid_o
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);
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logic flag;
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logic [3:0] flag_shift;
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logic kclkf, kdataf;
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logic [3:0] cnt;
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assign keycode_valid_o = flag_shift[0] && !flag_shift[2];
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debouncer debounce(
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.clk(clk_i),
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.I0(kclk_i),
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.I1(kdata_i),
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.O0(kclkf),
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.O1(kdataf)
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);
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always@(posedge clk_i) begin
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if(rst_i) begin
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flag_shift <= '0;
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end
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else begin
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flag_shift <= {flag_shift[2:0], flag};
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end
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end
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always_ff @(negedge kclkf or posedge rst_i)begin
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if(rst_i) begin
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cnt <= '0;
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end
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else if (cnt <= 9) begin
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cnt <= cnt + 1;
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end
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else begin
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cnt <= '0;
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end
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end
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always_ff @(negedge kclkf or posedge rst_i) begin
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if(rst_i) begin
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keycode_o <= '0;
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end
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else begin
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case(cnt)
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1:keycode_o[0]<=kdataf;
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2:keycode_o[1]<=kdataf;
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3:keycode_o[2]<=kdataf;
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4:keycode_o[3]<=kdataf;
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5:keycode_o[4]<=kdataf;
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6:keycode_o[5]<=kdataf;
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7:keycode_o[6]<=kdataf;
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8:keycode_o[7]<=kdataf;
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default: keycode_o <= keycode_o;
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endcase
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end
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end
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assign flag = cnt == 9;
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endmodule
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module debouncer(
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input logic clk,
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input logic I0,
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input logic I1,
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output logic O0,
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output logic O1
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);
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logic [4:0]cnt0, cnt1;
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logic Iv0=0,Iv1=0;
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logic out0, out1;
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always_ff @(posedge(clk))begin
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if (I0==Iv0) begin
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if (cnt0==19)O0<=I0;
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else cnt0<=cnt0+1;
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end
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else begin
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cnt0<=5'd0;
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Iv0<=I0;
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end
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if (I1==Iv1)begin
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if (cnt1==19)O1<=I1;
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else cnt1<=cnt1+1;
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end
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else begin
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cnt1<=5'd0;
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Iv1<=I1;
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end
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end
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endmodule
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