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50 lines
1.2 KiB
Systemverilog
50 lines
1.2 KiB
Systemverilog
//////////////////////////////////////////////////////////////////////////////////
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// Company: MIET
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// Engineer: Andrei Solodovnikov
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// Module Name: tb_riscv_unit
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// Project Name: RISCV_practicum
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// Target Devices: Nexys A7-100T
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// Description: tb for riscv unit with irq support
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//////////////////////////////////////////////////////////////////////////////////
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module tb_irq_unit();
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reg clk;
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reg rst;
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riscv_unit unit(
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.clk_i(clk),
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.rst_i(rst)
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);
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initial begin
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repeat(1000) begin
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@(posedge clk);
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end
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$fatal(1, "Test has been interrupted by watchdog timer");
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end
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initial clk = 0;
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always #10 clk = ~clk;
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initial begin
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$display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop();
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unit.irq_req = 0;
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rst = 1;
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#20;
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rst = 0;
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repeat(20)@(posedge clk);
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unit.irq_req = 1;
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while(unit.irq_ret == 0) begin
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@(posedge clk);
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end
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unit.irq_req = 0;
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repeat(20)@(posedge clk);
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$display("\n The test is over \n See the internal signals of the module on the waveform \n");
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$finish;
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end
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endmodule
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