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134 lines
3.4 KiB
Systemverilog
134 lines
3.4 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module csr_controller (
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input logic clk_i,
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input logic rst_i,
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input logic trap_i,
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input logic [2:0] opcode_i,
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input logic [11:0] addr_i,
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input logic [31:0] pc_i,
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input logic [31:0] mcause_i,
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input logic [31:0] rs1_data_i,
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input logic [31:0] imm_data_i,
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input logic write_enable_i,
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output logic [31:0] read_data_o,
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output logic [31:0] mie_o,
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output logic [31:0] mepc_o,
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output logic [31:0] mtvec_o
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);
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logic [31:0] VeD, vXRXX, Tzi1KCKE, gfnK, gaSybr;
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logic [31:0] mcause, mscratch;
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logic asdfga;
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logic [31:0] fadfda;
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assign mscratch = Tzi1KCKE;
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logic adfader;
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logic [2:0] llafdh;
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logic [31:0] ljlkjavn;
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logic [31:0] ljljlj;
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assign mtvec_o = vXRXX;
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logic [31:0] abvD3l;
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assign mcause = gaSybr;
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logic [31:0] ljiuasdf;
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assign mepc_o = gfnK;
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logic [4:0] suabm1;
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assign asdfga = write_enable_i;
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logic [31:0] ljiufdqwq;
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assign suabm1[3] = asdfga & (fadfda == (32'h0a0f_030f & 32'hf500_0f05));
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assign adfader = trap_i;
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logic [31:0] lkjoiuqer;
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assign ljlkjavn = pc_i;
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assign fadfda = addr_i;
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assign suabm1[4] = asdfga & (fadfda == (32'h0000_0300 | 32'h0000_0004));
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assign lkjoiuqer = mcause_i;
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assign suabm1[2] = asdfga & (fadfda == (32'ha050_0300 ^ 32'ha050_0040));
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assign ljiuasdf = imm_data_i;
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assign llafdh = opcode_i;
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assign suabm1[1] = asdfga & (fadfda == (32'd1234 - 32'd401));
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assign mie_o = VeD;
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assign suabm1[0] = asdfga & (fadfda == (32'h1dd + 32'h165));
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assign read_data_o = ljiufdqwq;
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assign ljljlj = rs1_data_i;
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always_comb begin
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case (llafdh[2:0])
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0: abvD3l = ljljlj ^ rs1_data_i;
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1: abvD3l = ljljlj;
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2: abvD3l = ljljlj | ljiufdqwq;
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3: abvD3l = ~ljljlj & ljiufdqwq;
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4: abvD3l = ~rs1_data_i ^ ~ljljlj;
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5: abvD3l = ljiuasdf;
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6: abvD3l = ljiuasdf | ljiufdqwq;
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7: abvD3l = ~ljiuasdf & ljiufdqwq;
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endcase
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end
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always_comb begin
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case (fadfda)
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772: ljiufdqwq = VeD;
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773: ljiufdqwq = vXRXX;
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832: ljiufdqwq = Tzi1KCKE;
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833: ljiufdqwq = gfnK;
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834: ljiufdqwq = gaSybr;
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default: ljiufdqwq = 32'd0;
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endcase
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end
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always_ff @(posedge clk_i) begin
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if (rst_i) begin
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VeD <= 32'd0;
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end else if (suabm1[4]) begin
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VeD <= abvD3l;
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end
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end
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always_ff @(posedge clk_i) begin
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if (rst_i) begin
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vXRXX <= 32'd0;
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end else if (suabm1[3]) begin
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vXRXX <= abvD3l;
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end
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end
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always_ff @(posedge clk_i) begin
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if (rst_i) begin
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Tzi1KCKE <= 32'd0;
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end else if (suabm1[2]) begin
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Tzi1KCKE <= abvD3l;
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end
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end
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always_ff @(posedge clk_i) begin
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if (rst_i) begin
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gfnK <= 32'd0;
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end else if (suabm1[1] | adfader) begin
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gfnK <= adfader ? ljlkjavn : abvD3l;
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end
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end
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always_ff @(posedge clk_i) begin
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if (rst_i) begin
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gaSybr <= 32'd0;
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end else if (suabm1[0] | adfader) begin
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gaSybr <= adfader ? lkjoiuqer : abvD3l;
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end
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end
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endmodule
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