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007889f849
Замена reg и wire, исправление нейминга сигналов, способов установки задержек, а также уменьшен интервал вводимых чисел для уменьшения длины временной диаграммы.
50 lines
1.3 KiB
Systemverilog
50 lines
1.3 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Nikita Bulavin
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* Email(s) : nekkit6@edu.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module lab_04_tb_CYBERcobra();
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logic [31:0] OUT;
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logic clk;
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logic rst;
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logic [15:0] sw_i;
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CYBERcobra DUT(
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.clk_i(clk),
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.rst_i(rst),
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.sw_i (sw_i),
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.out_o(OUT)
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);
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initial clk <= 0;
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always #5ns clk = ~clk;
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initial begin
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logic [15:0] count_num;
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$display("Test has been started");
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rst = 1'b1;
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repeat(2)@(posedge clk);
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rst = 1'b0;
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count_num = $urandom_range(5, 10);
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sw_i = count_num;
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repeat(count_num * 2 + 15) begin
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@(posedge clk);
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end
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$display("\nThe test is over.");
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$display("See the internal signals of the CYBERcobra on the waveform");
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$finish;
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@(posedge clk);
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$display("You're trying to run simulation that has finished.");
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$display("Aborting simulation.");
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$fatal();
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end
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endmodule
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