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a28002e681
* WIP: APS cumulative update * Update How FPGA works.md * Перенос раздела "Последовательностная логика" в отдельный док * Исправление картинки * Исправление оформления индексов * Переработка раздела Vivado Basics * Добавление картинки в руководство по созданию проекта * Исправление ссылок в анализе rtl * Обновление изображения в sequential logic * Исправление ссылок в bug hunting * Исправление ссылок * Рефактор руководства по прошивке ПЛИС * Mass update * Update fig_10 * Restore fig_02
49 lines
1.3 KiB
Systemverilog
49 lines
1.3 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module lab_11_tb_processor_system();
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reg clk;
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reg rst;
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processor_system system(
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.clk_i(clk),
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.rst_i(rst)
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);
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initial begin
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repeat(1000) begin
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@(posedge clk);
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end
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$fatal(1, "Test has been interrupted by watchdog timer");
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end
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initial clk = 0;
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always #10 clk = ~clk;
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initial begin
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$display( "\nTest has been started");
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system.irq_req = 0;
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rst = 1;
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#40;
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rst = 0;
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repeat(20)@(posedge clk);
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system.irq_req = 1;
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while(system.irq_ret == 0) begin
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@(posedge clk);
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end
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system.irq_req = 0;
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repeat(20)@(posedge clk);
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$display("\n The test is over \n See the internal signals of the module on the waveform \n");
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$finish;
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end
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endmodule
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