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94 lines
3.2 KiB
Systemverilog
94 lines
3.2 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module lab_16_tb_coremark();
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import bluster_pkg::*;
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logic clk100mhz_i;
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logic aresetn_i;
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logic rx_i;
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logic tx_o;
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logic clk_i;
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logic rst_i;
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logic core_reset;
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assign aresetn_i = !rst_i;
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assign core_reset = DUT.core.rst_i;
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logic rx_busy, rx_valid, tx_busy, tx_valid;
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logic [7:0] rx_data, tx_data;
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always #50ns clk_i = !clk_i;
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always #5ns clk100mhz_i = !clk100mhz_i;
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byte coremark_msg[103];
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integer coremark_cntr;
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initial begin
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$timeformat(-9, 2, " ns", 3);
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clk100mhz_i = 0;
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clk_i = 0;
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rst_i <= 0;
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@(posedge clk_i);
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rst_i <= 1;
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repeat(2) @(posedge clk_i);
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rst_i <= 0;
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finish_programming(clk_i, tx_valid, tx_busy, core_reset, tx_data);
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coremark_cntr = 0;
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coremark_msg = {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32};
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forever begin
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@(posedge clk_i);
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if(rx_valid) begin
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if((rx_data == 10) | (rx_data == 13)) begin
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$display("%s", coremark_msg);
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coremark_cntr = 0;
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coremark_msg = {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32};
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end
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else begin
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coremark_msg[coremark_cntr] = rx_data;
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coremark_cntr++;
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end
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end
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end
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end
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initial #500ms $finish();
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processor_system DUT(
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.clk_i (clk100mhz_i),
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.resetn_i (aresetn_i),
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.rx_i (rx_i),
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.tx_o (tx_o)
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);
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uart_rx rx(
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.clk_i (clk_i ),
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.rst_i (rst_i ),
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.rx_i (tx_o ),
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.busy_o (rx_busy ),
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.baudrate_i (17'd115200 ),
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.parity_en_i(1'b1 ),
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.stopbit_i (1'b1 ),
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.rx_data_o (rx_data ),
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.rx_valid_o (rx_valid )
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);
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uart_tx tx(
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.clk_i (clk_i ),
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.rst_i (rst_i ),
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.tx_o (rx_i ),
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.busy_o (tx_busy ),
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.baudrate_i (17'd115200 ),
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.parity_en_i(1'b1 ),
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.stopbit_i (1'b1 ),
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.tx_data_i (tx_data ),
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.tx_valid_i (tx_valid )
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);
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endmodule
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