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104 lines
2.7 KiB
Systemverilog
104 lines
2.7 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module lab_13_tb_processor_system();
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import peripheral_pkg::*;
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logic clk_i;
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logic resetn;
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logic [15:0] sw_i;
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logic [15:0] led_o;
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logic ps2_clk;
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logic ps2_dat;
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logic [ 6:0] hex_led_o;
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logic [ 7:0] hex_sel_o;
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logic rx_i;
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logic tx_o;
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initial begin clk_i = 0; end
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always #5ns clk_i = ~clk_i;
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initial #4ms $finish();
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initial begin
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resetn = 1;
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repeat(20)@(posedge clk_i);
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resetn = 0;
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repeat(20) @(posedge clk_i);
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resetn = 1;
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end
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processor_system DUT(
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.clk_i (clk_i ),
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.resetn_i (resetn ),
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.sw_i (sw_i ),
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.led_o (led_o ),
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.kclk_i (ps2_clk ),
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.kdata_i (ps2_dat ),
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.hex_led_o(hex_led_o),
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.hex_sel_o(hex_sel_o),
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.rx_i (rx_i ),
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.tx_o (tx_o )
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);
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initial begin: sw_block
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sw_i = 16'd0;
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repeat(1000) @(posedge clk_i);
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sw_i = 16'hdead;
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repeat(1000) @(posedge clk_i);
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sw_i = 16'h5555;
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repeat(1000) @(posedge clk_i);
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sw_i = 16'hbeef;
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repeat(1000) @(posedge clk_i);
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sw_i = 16'haaaa;
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end
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initial begin: ps2_initial_block
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ps2_clk = 1'b1;
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ps2_dat = 1'b1;
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repeat(1000) @(posedge clk_i);
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ps2_send_scan_code(8'h1C, ps2_clk, ps2_dat);
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repeat(1000) @(posedge clk_i);
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ps2_send_scan_code(8'hf0, ps2_clk, ps2_dat);
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repeat(1000) @(posedge clk_i);
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ps2_send_scan_code(8'h1C, ps2_clk, ps2_dat);
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repeat(1000) @(posedge clk_i);
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ps2_send_scan_code(8'h32, ps2_clk, ps2_dat);
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repeat(1000) @(posedge clk_i);
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ps2_send_scan_code(8'hf0, ps2_clk, ps2_dat);
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repeat(1000) @(posedge clk_i);
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ps2_send_scan_code(8'h32, ps2_clk, ps2_dat);
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repeat(1000) @(posedge clk_i);
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ps2_send_scan_code(8'h21, ps2_clk, ps2_dat);
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repeat(1000) @(posedge clk_i);
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ps2_send_scan_code(8'hf0, ps2_clk, ps2_dat);
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repeat(1000) @(posedge clk_i);
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ps2_send_scan_code(8'h21, ps2_clk, ps2_dat);
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end
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initial begin: uart_rx_initial_block
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rx_i = 1'b1;
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repeat(1000) @(posedge clk_i);
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uart_rx_send_char(8'h1c, 115200, rx_i);
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repeat(1000) @(posedge clk_i);
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uart_rx_send_char(8'h0D, 115200, rx_i);
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repeat(1000) @(posedge clk_i);
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uart_rx_send_char(8'h0D, 115200, rx_i);
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repeat(1000) @(posedge clk_i);
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uart_rx_send_char(8'h7F, 115200, rx_i);
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repeat(1000) @(posedge clk_i);
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uart_rx_send_char(8'h7F, 115200, rx_i);
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end
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endmodule
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