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18 lines
773 B
Systemverilog
18 lines
773 B
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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package memory_pkg;
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localparam INSTR_MEM_SIZE_BYTES = 512;
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localparam INSTR_MEM_SIZE_WORDS = INSTR_MEM_SIZE_BYTES / 4;
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localparam DATA_MEM_SIZE_BYTES = 512;
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localparam DATA_MEM_SIZE_WORDS = DATA_MEM_SIZE_BYTES / 4;
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endpackage |