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* Имя порта совпадало с именем типа * Update Labs/13. Peripheral units/peripheral_pkg.sv --------- Co-authored-by: Andrei Solodovnikov <VoultBoy@yandex.ru>
42 lines
1.5 KiB
Systemverilog
42 lines
1.5 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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package peripheral_pkg;
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localparam DMEM_ADDR_HIGH = 8'h00;
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localparam SW_ADDR_HIGH = 8'h01;
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localparam LED_ADDR_HIGH = 8'h02;
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localparam PS2_ADDR_HIGH = 8'h03;
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localparam HEX_ADDR_HIGH = 8'h04;
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localparam RX_ADDR_HIGH = 8'h05;
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localparam TX_ADDR_HIGH = 8'h06;
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localparam VGA_ADDR_HIGH = 8'h07;
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localparam TIMER_ADDR_HIGH = 8'h08;
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task automatic ps2_send_scan_code(input logic [7:0] code, ref logic ps2_clk, ref logic ps2_dat);
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logic [11:0] data = {2'b11, !(^code), code, 1'b0};
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for(int i = 0; i < 11; i++) begin
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ps2_dat = data[i];
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#15us;
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ps2_clk = 1'b0;
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#15us;
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ps2_clk = 1'b1;
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end
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endtask
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task automatic uart_rx_send_char(input logic [7:0] character, input logic [31:0] baudrate, ref logic tx);
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logic [11:0] data = {2'b11, (^character), character, 1'b0};
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for(int i = 0; i < 12; i++) begin
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tx = data[i];
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#(1s/baudrate);
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end
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endtask
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endpackage |