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86 lines
2.3 KiB
Systemverilog
86 lines
2.3 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module lab_01_tb_fulladder32();
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logic [31:0] tb_a_i;
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logic [31:0] tb_b_i;
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logic tb_carry_i;
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logic tb_carry_o;
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logic [31:0] tb_sum_o;
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logic clk = 0;
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always #5ns clk = ~clk;
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int err_cnt = 0;
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fulladder32 DUT (
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.a_i(tb_a_i),
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.b_i(tb_b_i),
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.sum_o(tb_sum_o),
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.carry_i(tb_carry_i),
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.carry_o(tb_carry_o)
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);
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initial begin
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$display("Test has been started");
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sequential_add_test();
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random_test();
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$display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
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$finish();
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#5;
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$display("You're trying to run simulation that has finished. Aborting simulation.");
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$fatal();
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end
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task sequential_add_test();
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@(posedge clk);
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tb_a_i = 0;
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tb_b_i = 0;
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tb_carry_i = 0;
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@(posedge clk);
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for(int i = 0; i < 16; i++) begin
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tb_a_i += 256;
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for(int j = 0; j < 16; j++) begin
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tb_b_i += 256;
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tb_carry_i = ~tb_carry_i;
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@(posedge clk);
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end
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end
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endtask
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task random_test();
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repeat(1e4) begin
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tb_a_i = $urandom();
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tb_b_i = $urandom();
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tb_carry_i = $urandom_range(1);
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@(posedge clk);
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end
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endtask
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logic [32:0] reference;
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assign reference = {1'b0, tb_a_i} + {1'b0, tb_b_i} + tb_carry_i;
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sum_check: assert property (
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@(negedge clk)
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reference === {tb_carry_o, tb_sum_o}
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)
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else begin
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err_cnt++;
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$error("\noperands : a_i = 0x%08h, b_i = 0x%08h, carry_i = %b\nyour res : sum = 0x%08h, carry_o = %b\nreference: sum = 0x%08h, carry_o = %b",
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tb_a_i, tb_b_i, tb_carry_i, tb_sum_o, tb_carry_o, reference[31:0], reference [32]);
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if(err_cnt == 10) begin
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$display("\nTest has been stopped after 10 errors");
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$stop();
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end
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end
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endmodule
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