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44 lines
1.4 KiB
Systemverilog
44 lines
1.4 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module data_mem (
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input logic clk_i,
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input logic mem_req_i,
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input logic write_enable_i,
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input logic [ 3:0] byte_enable_i,
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input logic [31:0] addr_i,
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input logic [31:0] write_data_i,
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output logic [31:0] read_data_o,
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output logic ready_o
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);
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assign ready_o = 1'b1;
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import memory_pkg::DATA_MEM_SIZE_WORDS;
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logic [31:0] ram [DATA_MEM_SIZE_WORDS];
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logic [31:0] addr;
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assign addr = addr_i[2+:$clog2(DATA_MEM_SIZE_WORDS)];
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always_ff @(posedge clk_i) begin
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if(mem_req_i & !write_enable_i) begin
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read_data_o <= ram[addr];
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end
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end
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always_ff @(posedge clk_i) begin
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if(mem_req_i & write_enable_i) begin
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if(byte_enable_i[0]) ram[addr][ 7: 0] = write_data_i[ 7: 0];
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if(byte_enable_i[1]) ram[addr][15: 8] = write_data_i[15: 8];
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if(byte_enable_i[2]) ram[addr][23:16] = write_data_i[23:16];
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if(byte_enable_i[3]) ram[addr][31:24] = write_data_i[31:24];
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end
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end
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endmodule
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